Phytec phyFLEX-i.MX 6 - SPI Interface Details

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
50  PHYTEC Messtechnik GmbH 2013 L-773e_2
8.6 SPI Interface
The Serial Peripheral Interface (SPI) interface is a four-wire,
bidirectional serial bus that provides a simple and efficient method for
data exchange among devices. The phyFLEX provides two SPI
interfaced on the phyFLEX-fix connector X1. The SPI interfaces
provide three respectively two chip select signals. The Enhanced
Configurable SPI (ECSPI) of the i.MX 6 has five separate modules
(ECSPI1, ECSPI2, ECSPI3, ECSPI4 and ECSPI5) which support data
rates of up to 20 Mbit/s. The interface signals of the third and fifth
module (ECSPI3, ECSPI5) are made available on the phyFLEX-
Connector. This module is master/slave configurable. The following
table lists the SPI signals on the phyFLEX-Connector:
Pin # Signal ST Voltage Domain Description
X1A21 X_SPI0_MOSI O VDD_3V3_LOGIC
SPI0 master
output/slave input
X1A23 X_SPI0_MISO I VDD_3V3_LOGIC
SPI0 master
input/slave output
X1A24 X_SPI0_CSBOOT O VDD_3V3_LOGIC
SPI0 chip select
BOOT
X1A25 X_SPI0_CS0 O VDD_3V3_LOGIC SPI0 chip select 0
X1A26 X_SPI0_CS1 O VDD_3V3_LOGIC SPI0 chip select 1
X1A27 reference-voltage REF_O VDD_3V3_LOGIC
SPI0 reference
voltage
X1A29 X_SPI0_CLK O VDD_3V3_LOGIC SPI0 clock signal
X1A30 X_SPI1_CS0 O VDD_3V3_LOGIC SPI1 chip select 0
X1A31 X_SPI1_MOSI O VDD_3V3_LOGIC
SPI1 master
output/slave input
X1A32 X_SPI1_MISO I VDD_3V3_LOGIC
SPI1 master
input/slave output
X1A33 reference-voltage REF_O VDD_3V3_LOGIC
SPI1 reference
voltage
X1A35 X_SPI1_CLK O VDD_3V3_LOGIC SPI1 clock signal
X1A36 X_SPI1_CS1 O VDD_3V3_LOGIC SPI1 chip select 1
Table 21: SPI Interface Signal Location
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