D(0:31)
A(0:25)
CS2~
CS4~
CS5~
RD/WR~
RAS~
RD~
WE0~
WE1~
WE2~
WE3~
RESM~
TMS
TDO
COM2_RXD
COM2_TXD
COM1_TXD
COM1_RXD
DACK0
DREQ0~
RST_SYS~
TRST
FWE
CKIO
BS~
CS0~
LED1_RED
LED2_RED
PFO~
LCLK
CS6~
IRQ4~
TRANSPORT_CL~
CABLE~
SPARE~
MODEL30K~
WDT_CP
LED3_GRN
LED4_GRN
FPGA_DONE
FPGA_RES
TDI
IRQ5~
IRQ7~
IRQ6~
CS3~
CS1~
CKE
TCK
ASEBRK-/BRKACK
IRL0~
IRL1~
IRL2~
IRL3~
INIT_FPGA~
PROG_FPGA~
FPGA_CCLK
BREQ~
RDY~
CFG2
I2C0_SCL
I2C0_SDA
CFG1
RST_SYS~
FEEDER_CL~
FPGA_WRITE
STACKER_FULL~
OL_LITE
DACK1
DREQ1~
BACK~
DRAK1
FPGA_CS~
XL_PD(6)
XL_PD(1)
XL_PD(0:7)
)))))
D(30)
D(29)
D(28)
D(27)
D(26)
D(25)
D(24)
D(23)
D(22)
D(21)
D(20)
D(19)
D(18)
D(17)
D(16)
D(15)
D(14)
D(13)
D(12)
D(11)
D(10)
D(9)
D(8)
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
A(1)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
A(24)
A(25)
A(0)
A(2)
0.1uF
C125
0.1uF
C128
0.01uF
C133
0.1uF
C184
0.01uF
C185
0.1uF
C159
0.01uF
C160
0.1uF
C136
0.01uF
C137
0.1uF
C135
0.01uF
C134
0.1uF
C148
0.01uF
C147
0.1uF
C183
0.01uF
C182
0.1uF
C166
0.01uF
C165
0.1uF
C123
0.01uF
C124
0.1uF
C152
0.01uF
C151
0.1uF
C168
0.01uF
C167
0.1uF
C172
0.01uF
C171
0.1uF
C150
0.01uF
C149
0.1uF
C154
0.01uF
C153
0.1uF
C170
0.01uF
C169
47uF
C39
47uF
C40
NOTES:
1. UNLESS OTHERWISE SPECIFIED:
2. FOR ASSEMBLY DRAWING SEE DRAWING
ALL CAPACITANCE ARE IN uf (MICROFARAD).
ALL RESISTORS ARE IN OHMS, +/-.5 AND 1/10 WATT.
(2)
(1),(3)
(1),(3)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
10Kohms
R56
10Kohms
R60
10Kohms
R61
10Kohms
R58
10Kohms
R57
0.1uF
C13
DEBUG NMI
2
261-1412
1
J7
(4)
(4)
(4)
(4)
30pF
C16
30pF
C17
(6)
(6)
(6)
(6)
(3)
(3)
(3)
3
4
(9),(3),(1),(1),(2)
10Kohms
R236
10Kohms
R233
Time:09:00:23 AM Date:05/25/2007
Page: 01 of 10
NONE
DATE
DRAWN
APPROVED
TITLE
MODEL
PART NO
DATE
SCALE
CHANGE ORDER NO
PRODUCT
CODE
NEXT ASSEMBLY REQ
THIRD ANGLE
PROJECTION
DO NOT SCALE THIS DRAWING
SIZE
DWG
ALL OTHER CHARACTERISTICS
MINOR
MAJOR
CRITICAL
PER PB B1525
CLASSIFICATION OF CHARACTERISTICS
+
+
-
-
-
+
THREE PLACE DECIMALS
TWO PLACE DECIMALS
ONE PLACE DECIMALS
0.005
0.01
0.03
TOLERANCES
UNLESS OTHERWISE SPECIFIED:
WORKMANSHIP PER PB PROCEDURE B1850
Pitney Bowes
D
C.O. NO.
DATE
BY
CHKCHANGE DESCRIPTION
SYMLOC
This document/data record is the property of Pitney Bowes
Inc. and contains PROPRIETARY and CONFIDENTIAL information
and is not to be copied.
DWG
NO.
(1),(2)
33ohms
R123
10Kohms
R76
(4)
0.01uF
C126
(5)
(5)
(5)
(5)
(5)
(5)
TP30
WW POST
Black
TP26
Yellow
TP25
1
J8
9
13
2
11
5
6
14
7
8
10
12
72
SWITCH
81
S1
54
63
10Kohms
R104
10Kohms
R93
10Kohms
R263
10Kohms
R94
10Kohms
R111
10Kohms
R113
10Kohms
R96
10Kohms
R266
10Kohms
R264
10Kohms
R243
10Kohms
R102
10Kohms
R84
10Kohms
R249
10Kohms
R250
10Kohms
R272
10Kohms
R248
10Kohms
R265
10Kohms
R95
10Kohms
R267
10Kohms
R268
10Kohms
R262
10Kohms
R112
10Kohms
R232
10Kohms
R55
10Kohms
R103
TP34
WW POST
TP33
WW POST
TP32
WW POST
WW POST
TP12
WW POST
TP11
TP36
WW POST
TP31
WW POST
WW POST
TP20
WW POST
TP18
TP10
WW POST
TP35
WW POST
WW POST
TP9
WW POST
TP7
WW POST
TP8
WW POST
TP5
WW POST
TP19
WW POST
TP6
WW POST
TP17
WW POST
TP4
WW POST
TP1
Black
TP28
Yellow
TP27
10Kohms
R59
(4)
(1),(5)
(1),(5)
(1),(5)
(3)
(4)
(4)
(4)
(4)
(4),(4),(5),(1)
XL_PD(4)
XL_PD(3)
XL_PD(2)
XL_PD(7)
(4)
(4)
XL_PD(0)
XL_PD(5)
(1),(3)
(4)
(4)
10Kohms
R219
10Kohms
R220
10Kohms
R221
10Kohms
R222
10Kohms
R110
100pF
C20
(1)
4.7Kohms
R75
4.7Kohms
R246
4.7Kohms
R245
4.7Kohms
R87
4.7Kohms
R86
4.7Kohms
R244
4.7Kohms
R92
4.7Kohms
R99
4.7Kohms
R237
10ohms
R78
10Kohms
R73
10Kohms
R74
10Kohms
R235
10Kohms
R242
10Kohms
R241
10Kohms
R240
10ohms
R77
10ohms
R85
10ohms
R79
10uF
C19
10uF
C26
10uF
C21
0.1uF
C127
1
J13
5
11
3
7
9
10
8
4
12
6
2
10Kohms
R227
10Kohms
R226
200-1082
16.000 MHZ
2
1
Y1
HD6417760BP200ADV
HD6417760BP200ADV
BGA256_20x20_1MM
U13
EXT CRYSTAL
MFI MODE
LITTLE ENDIAN
MODE 3
16 BIT FLASH
K17
B2
B4
C3
B18
C19
D9
D11
D13
D15
E17
H4
J17
K4
M4
M17
N17
U5
U8
U10
U11
U12
U16
W2
W19
D7
D14
G4
G17
P4
P17
U7
U14
K18
A3
A4
B3
A19
B20
C9
C11
C13
E18
H3
J18
K3
M3
M18
N18
V3
V5
V8
V10
V11
V12
V16
V18
C7
C14
G3
G18
P3
P18
V7
V14
A2
E2
E1
C18
D20
C20
B19
A20
D10
C10
C12
D12
C15
D8
D6
D3
C6
D2
B5
C5
A5
A11
A12
A14
A13
A10
B12
B13
B15
B14
B11
A16
B16
A15
B1
H20
H19
J20
J19
K20
C1
B10
D5
T2
T1
R2
P1
R1
N1
M1
L1
K1
J1
H1
G1
F1
N2
M2
L2
K2
J2
H2
G2
F2
P2
H18
H17
G19
G20
A17
B17
C16
D17
D16
F18
F17
F20
F19
M19
M20
N19
N20
A6
B7
A7
B6
D4
C2
A1
E20
E19
D18
C17
D1
D19
A18
A9
B9
A8
B8
T20
R20
P20
T19
R19
P19
E3
T3
E4
F4
C8
L17
L18
L19
L20
K19
XTAL
STATUS1
STATUS0
BACK~
BS~
RESERVED/AUDSYNC
RESERVED/AUDCK
RESERVED/AUDATA(1)
RESERVED/AUDATA(2)
RESERVED/AUDATA(3)
CAN1_TX/AUDATA(1)
CAN0_TX/AUD ATA(0)
DCK
DRAK1
DRAK0
DACK1
DACK0
TDO
USB_PENC
SCIF2_TXD
SCIF1_TXD
SCIF0_TXD
HAC_RES~
CKE
CKIO
WE3~/DQM3/ICIOWR~
WE2~/DQM2/ICIORD~
WE1~/DQM1
WE0~/DQM0/REG~
RD~/CASS~/FRAME~
RAS~
RD/WR~
CS6~
CS5~
CS4~
CS3~
CS2~
CS1~
CS0~
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D7
D8
D6
D5
D4
D3
D2
D1
D0
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MD0
MD1
MD2
MD3/CE2A~
MD4/CE2B~
MD5
MD6/IOIS16~
MD7
MD8
RESET~
MRESET~
RDY~
BREQ~
CA
EXTAL
MFI-INT~/LCD_CLK
MFI-CS~/LCD_DON
MFI-E/LCD_CL1
MFI-MD/LCD_CL2
MFI-RS/LCD_M_DISP
MFI-RW/LCD_FLM
MFI-D0/LCD_DATA0
MFI-D1/LCD_DATA1
MFI-D2/LCD_DATA2/IRQ6~
MFI-D3/LCD_DATA3/IRQ7~
MFI-D4/LCD_DATA4/DREQ2~
MFI-D5/LCD_DATA5/DRAK2/DACK2
MFI-D6/LCD_DATA6/DREQ3~
MFI-D7/LCD_DATA7/DRAK3/DACK3
MFI-D8/LCD_DATA8
MFI-D9/LCD_DATA9
MFI-D10/LCD_DATA10
MFI-D11/LCD_DATA11
MFI-D12/LCD_DATA12
MFI-D13/LCD_DATA13
MFI-D14/LCD_DATA14
MFI-D15/LCD_DATA15
VCPWC/IRQ4~
VEPWC/IRQ5~
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
SSI0_SCK/HAC_SD_IN0/BS2~
SSI0_WS/HAC_SYNC0
SSI0_SDATA/HAC_SD_OUT0
SSI1_WS/HAC_S YNC1
SSI1_SCK/HAC_SD_IN1
SSI1_SDATA/HAC_SD_OUT1
CMT_CTR0/TCLK
CMT_CTR1
CMT_CTR2
CMT_CTR3
SCIF0_CLK
SCIF1_CLK
SCIF1_CTS~
SCIF1_RTS~
SCIF2_CLK
SCIF2_CTS~
SCIF2_RTS~
USB_DP
USB_DM
ASEBRK~/BRKACK
HAC_BIT_CLK0
HAC_BIT_CLK1
SCIF0_RXD
SCIF1_RXD
SCIF2_RXD
UCLK
USB_OVC~
TCK
TMS
TDI
TRST~
NMI
IRL0~
IRL1~
IRL2~
IRL3~
DREQ0~
DREQ1~
HSPI_RX
HSP1_TX/SIM_D/MCDAT
HSP1_CLK/SIM_CLK/MCCLK
HSP1_CS~/SIM_RST/MCCMD
CAN0_NERR/AUDCK
CAN0_RX/AUDATA(2)
CAN1_NERR/AUDSYNC
CAN1_RX/AUDATA(3)
ADTRG~/AUDATA(0)
AN0
AN1
AN2
AN3
VSS
VSSQ
AVSS-ADC
VSS-CPG
VSS-PLL3
VSS-PLL2
VSS-PLL1
AVCC-ADC
VDD-CPG
VDD-PLL3
VDD-PLL2
VDD-PLL1
VDDQVDD
(3)
74VHC14
GROUND = GND
VCC = +3.3V
12
U1
GROUND = GND
VCC = +3.3V
34
U1
47uF
C121
7.5Kohms
R224
BAT54S
CR6
(4)
(4)
(4)
(8)
(4)
(4)
(4)
(4)
(4)
(1),(4),(8)
(4)
TP54
TP55
TP53
TP56
TP58
WW POST
THIS SHARED BUS IS USED TO PROGRAM THE FPGA, THEN FOR LCD/KEYBOARD I/O FROM FPGA
ADDED U45, CHANGED J15
CHG'D R76 TO 10K PULL-UP INSTEAD OF 1K PULLDOWN
KM YL
PRODUCTION RELEASE
9/15/06
C
WF82000
B
NOTE: PROCESSOR DECOUPLING
MUST BE AS CLOSE TO EACH PIN
AS POSSIBLE WITH SHORT WIDE
TRACES
NOTE: ALL
CRYSTAL LAYOUT
CONNECTIONS
AS SHORT
AS POSSIBLE
JTAG
A
3/13/06
YLKM
CONFIGURATION CONTROL DOCUMENT
REQUIRES UPDATING WHENEVER
THIS DOCUMENT IS REVISED
MD[0,1,2]: CLOCK MODE
MD[3,4,6]: CS0 BUS WIDTH
MD[5]: 1=LITTLE ENDIAN
MD[7]: 0=MFI MODE
MD[8]: 1=INTERNAL CLOCK
MAIN PROCESSOR
SCHEM, MAIN PROCESSOR BD, 22K/30K
WF92000
WFXX
CO11159
INITIAL BUILD
Do Not Populate:
R25 and R26 for
configuration
bits = 00
YLKM
3/13/06
REFCCWF82000
K. MINCKLER 3/13/06
WFXXYOUNG LEE 3/13/06
CO11159 WF92000
SECOND BUILD
DOUBLES AS FPGA_BUSY--->
PROGRAMMING CS ONLY--->
CO15516D
5/24/07
PRODUCTION RELEASE
YLKM
CHG'D R76 TO 10K BACK TO PULLDOWN
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