RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 137
Sep 22, 2011
Table 3-5. SFR List (1/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF00H Port register 0 P0 R/W
√ √ −
00H
FFF01H Port register 1 P1 R/W
√ √ −
00H
FFF02H Port register 2 P2 R/W
√ √ −
00H
FFF03H Port register 3 P3 R/W
√ √ −
00H
FFF04H Port register 4 P4 R/W
√ √ −
00H
FFF05H Port register 5 P5 R/W
√ √ −
00H
FFF06H Port register 6 P6 R/W
√ √ −
00H
FFF07H Port register 7 P7 R/W
√ √ −
00H
FFF08H Port register 8 P8 R/W
√ √ −
00H
FFF09H Port register 9 P9 R/W
√ √ −
00H
FFF0AH Port register 10 P10 R/W
√ √ −
00H
FFF0BH Port register 11 P11 R/W
√ √ −
00H
FFF0CH Port register 12 P12 R/W
√ √ −
Undefined
FFF0DH Port register 13 P13 R/W
√ √ −
Undefined
FFF0EH Port register 14 P14 R/W
√ √ −
00H
FFF0FH Port register 15 P15 R/W
√ √ −
00H
FFF10H TXD0/
SIO00
− √
FFF11H
Serial data register 00
−
SDR00 R/W
− −
√
0000H
FFF12H RXD0/
SIO01
− √
FFF13H
Serial data register 01
−
SDR01 R/W
− −
√
0000H
FFF14H TXD3/
SIO30
− √
FFF15H
Serial data register 12
−
SDR12 R/W
− −
√
0000H
FFF16H RXD3/
SIO31
− √
FFF17H
Serial data register 13
−
SDR13 R/W
− −
√
0000H
FFF18H
FFF19H
Timer data register 00 TDR00 R/W
− − √
0000H
FFF1AH
TDR01L
− √
00H
FFF1BH
Timer data register 01
TDR01H
TDR01 R/W
− √
√
00H
FFF1EH 10-bit A/D conversion result
register
ADCR R
− − √
0000H
FFF1FH 8-bit A/D conversion
result register
ADCRH R
− √ −
00H
FFF20H Port mode register 0 PM0 R/W
√ √ −
FFH
FFF21H Port mode register 1 PM1 R/W
√ √ −
FFH
FFF22H Port mode register 2 PM2 R/W
√ √ −
FFH
FFF23H Port mode register 3 PM3 R/W
√ √ −
FFH
FFF24H Port mode register 4 PM4 R/W
√ √ −
FFH
FFF25H Port mode register 5 PM5 R/W
√ √ −
FFH
FFF26H Port mode register 6 PM6 R/W
√ √ −
FFH
FFF27H Port mode register 7 PM7 R/W
√ √ −
FFH
FFF28H Port mode register 8 PM8 R/W
√ √ −
FFH
FFF29H Port mode register 9 PM9 R/W
√ √ −
FFH
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