Renesas RL78/G13 - Page 180

RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 161
Sep 22, 2011
Figure 3-45. Example of ES:[HL + byte], ES:[DE + byte]
OP code
byte
rp (HL/DE)
Memory
FFFFFH
00000H
Target memory
ES
Figure 3-46. Example of ES:word[B], ES:word[C]
r (B/C)
Memory
FFFFFH
00000H
Target memory
ES
OP code
Low Addr.
High Addr.
Figure 3-47. Example of ES:word[BC]
rp (BC)
Memory
FFFFFH
00000H
Target memory
ES
OP code
Low Addr.
High Addr.