RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 480
Sep 22, 2011
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0 RTCEN
IICA1EN
Note 1
ADCEN
IICA0EN
Note 2
SAU1EN
Note 3
SAU0EN
TAU1EN
Note 1
TAU0EN
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Notes 1. 80, 100, and 128-pin products only.
2. This is not provided in the 20-pin products.
3. This is not provided in the 20, 24, and 25-pin products.
Cautions 1. When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing
to a control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 0, 2, 12, and 14 (PM0, PM2, PM12, PM14),
port mode control registers 0, 12, and 14 (PMC0, PMC12, PMC14), and A/D port configuration
register (ADPC)).
2. Be sure to clear the following bits to 0.
20-pin products: bits 1, 3, 4, 6
24, 25-pin products: bits 1, 3, 6
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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