RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 481
Sep 22, 2011
(2) A/D converter mode register 0 (ADM0)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-3. Format of A/D Converter Mode Register 0 (ADM0)
ADCELV0
Note 1
LV1
Note 1
FR0
Note 1
FR1
Note 1
FR2
Note 1
ADMDADCS
A/D conversion operation control
Stops conversion operation
[When read]
Conversion stopped/standby status
ADCS
0
<0>123456<7>
ADM0
Address: FFF30H After reset: 00H R/W
Symbol
Specification of the A/D conversion channel selection mode
Select mode
Scan mode
ADMD
0
1
A/D voltage comparator operation control
Note 3
Stops A/D voltage comparator operation
Enables A/D voltage comparator operation
ADCE
0
1
Enables conversion operation
[When read
Note 2
]
While in the software trigger mode: Conversion operation status
While in the hardware trigger wait mode: Stabilization wait status + conversion
operation status
1
Notes 1. For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 11-3 A/D Conversion Time
Selection.
2. While in the software trigger mode or hardware trigger wait mode, the ADCS bit can be used as a status
flag for the conversion operation status. However, while in the hardware trigger no-wait mode, this bit
cannot be used as a status flag.
3. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage
comparator is controlled by the ADCS and ADCE bits, and it takes 1
μ
s from the start of operation for the
operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1
μ
s or more has elapsed from the
time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result.
Otherwise, ignore data of the first conversion.
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