RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 672
Sep 22, 2011
Figure 12-101. Reception Operation of LIN
LIN Bus
13-bit SBF
reception
SF
reception
ID
reception
Data
reception
Data
reception
Data
reception
Wakeup signal
frame
Sync break
field
Sync field Identification
field
Data filed Data filed Checksum
field
R
X
D2 (input)
Reception interrupt
(INTSR2)
Edge detection
(INTP0)
Capture
timer
Disable Enable
Disable Enable
<1>
<2>
<3>
<4>
<5>
Here is the flow of signal processing.
<1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
detected, enable reception of UART2 (RXE11 = 1) and wait for SBF reception.
<2> When the start bit of SBF is detected, reception is started and serial data is sequentially stored in the RXD2
register (= bits 7 to 0 of serial data register 11 (SDR11)) at the set baud rate. When the stop bit is detected, the
reception end interrupt request (INTSR2) is generated. When data of low levels of 11 bits or more is detected as
SBF, it is judged that SBF reception has been correctly completed. If data of low levels of less than 11 bits is
detected as SBF, it is judged that an SBF reception error has occurred, and the system returns to the SBF
reception wait status.
<3> When SBF reception has been correctly completed, start channel 7 of the timer array unit and measure the bit
interval (pulse width) of the sync field (see 6.7.5 Operation as input signal high-/low-level width
measurement).
<4> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART2 once and adjust (re-set) the baud
rate.
<5> The checksum field should be distinguished by software. In addition, processing to initialize UART2 after the
checksum field is received and to wait for reception of SBF should also be performed by software.
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