RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 716
Sep 22, 2011
Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2)
CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1)
0 The SCLA0 pin was detected at low level.
1 The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
• When the SCLA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SCLA0 pin is at high level
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0 The SDAA0 pin was detected at low level.
1 The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
• When the SDAA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SDAA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
PRS0 Division of the operation clock
0 Selects fCLK as operation clock.
1 Selects fCLK/2 as operation clock.
Caution The fastest operation frequency of the operation clock of the serial interface IICA is 20
MHz (Max.). If the f
CLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRS0 bit to 1.
Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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