RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 717
Sep 22, 2011
(6) IICA low-level width setting register 0 (IICWL0)
This register is used to set the low-level width (tLOW) and data hold time (tHD:DAT) of the SCLA0 pin signal that is
output by serial interface IICA. The data hold time is decided by value the higher 6 bits of IICWL register.
The IICWL0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWL0 register while operation of I
2
C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
For details about setting the IICWL0 register, see 13.4.2 Setting transfer clock by using IICWL0 and IICWH0
registers.
Figure 13-10. Format of IICA Low-Level Width Setting Register 0 (IICWL0)
Address: F0232H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWL0
Setting value of data hold time
(7) IICA high-level width setting register 0 (IICWH0)
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA.
The IICWH0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWH0 register while operation of I
2
C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
Figure 13-11. Format of IICA High-Level Width Setting Register 0 (IICWH0)
Address: F0233H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWH0
Remark For how to set the transfer clock by using the IICWL0 and IICWH0 registers, see 13.4.2 Setting
transfer clock by using IICWL0 and IICWH0 registers.
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