RL78/G13 CHAPTER 18 STANDBY FUNCTION
R01UH0146EJ0100 Rev.1.00 861
Sep 22, 2011
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 18-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Oscillation stabilization time
(check by using OSTC register)
Normal operation
(high-speed on-chip
oscillator clock)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Reset processing
Note
When high-speed on-chip oscillator clock is used as CPU clock
HALT
instruction
Reset signal
High-speed on-chip
oscillator clock
Normal operation
(high-speed on-chip
oscillator clock)
HALT mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
Reset processing
Note
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Reset
period
Normal operation mode
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation
stopped
Starting XT1 oscillation is
specified by software.
Reset processing
Note
Note Reset processing time: 387 to 720
μ
s (When LVD is used)
155 to 407
μ
s (When LVD off)
<R>
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