Sony MVC-FD83 - Camera Block Diagram 1

MVC-FD83/FD88
3-6
3-5
3-2. CAMERA BLOCK DIAGRAM 1
8.4 Vp-p
125 µsec
IC201 1, 2, 3 REC
8.4 Vp-p
1.2 Vp-p
5.0 Vp-p
4.3 Vp-p
125 µsec
125 µsec
83 nsec
83 nsec
IC201 4, 5, 6 REC
IC201 8 REC
IC201 !∞, !§ REC
IC201 !¢ REC
8.4 Vp-p
8.4 Vp-p
1.7 Vp-p
4.0 Vp-p
4.2 Vp-p
125 µsec
125 µsec
125 µsec
83 nsec
83 nsec
IC101 1, 3 REC
IC101 2, 4 REC
IC101 8 REC
IC101 !∞, !§ REC
IC101 !¢ REC
4.0 Vp-p
4.8 Vp-p
24.545451 MHz: NTSC
24.375 MHz: PAL
41 nsec
IC001 3 REC/PB
IC001 1 REC/PB
4.0 Vp-p
83 nsec
IC001 @∞ REC/PB
4.8 Vp-p
4.0 Vp-p
4.0 Vp-p
24.545451 MHz: NTSC
24.375 MHz: PAL
41 nsec
83 nsec
IC003 @∞ REC/PB
IC003 @§ REC/PB
IC003 #º REC/PB
1.2 Vp-p
4.4 Vp-p
125 µsec
83 nsec
IC004 @§ REC
IC004 !§ REC
4.0 Vp-p
16.384 MHz
IC503 $¡ REC/PB