General purpose timer (TIMx) UM0306
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13.5.9 Capture/compare enable register (TIMx_CCER)
Address offset: 20h
Reset value: 0000h
1514131211109876543210
Reserved CC4P CC4E Reserved CC3P CC3E Reserved CC2P CC2E Reserved CC1P CC1E
rw rw rw rw rw rw rw rw
Bits 15:14 Reserved, always read as 0.
Bit 13
CC4P: Capture/Compare 4 output Polarity.
refer to CC1P description
Bit 12
CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bits 11:10 Reserved, always read as 0.
Bit 9
CC3P: Capture/Compare 3 output Polarity.
refer to CC1P description
Bit 8
CC3E: Capture/Compare 3 output enable.
refer to CC1E description
Bits 7:6 Reserved, always read as 0.
Bit 5
CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
Bit 4
CC2E: Capture/Compare 2 output enable.
refer to CC1E description
Bits 3:2 Reserved, always read as 0.
Bit 1
CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for trigger or capture operations.
0: non-inverted: capture is done on a rising edge of IC1. When used as external
trigger, IC1 is non-inverted.
1: inverted: capture is done on a falling edge of IC1. When used as external trigger,
IC1 is inverted.
Bit 0
CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the
input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
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