ST ST32M103 Series User Manual

Controller area network (bxCAN) UM0306
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Bit 17
TXOK2: Transmission OK of Mailbox 2
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 2 has been
completed successfully. Please refer to Figure 124.
Bit 16
RQCP2: Request Completed Mailbox2
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ2
set in CAN_TMID2R register).
Clearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox
2.
Bit 15
ABRQ1: Abort Request for Mailbox 1
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 14:12 Reserved, forced by hardware to 0.
Bit 11
TERR1: Transmission Error of Mailbox1
This bit is set when the previous TX failed due to an error.
Bit 10
ALST1: Arbitration Lost for Mailbox1
This bit is set when the previous TX failed due to an arbitration lost.
Bit 9
TXOK1: Transmission OK of Mailbox1
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been
completed successfully. Please refer to Figure 124
Bit 8
RQCP1: Request Completed Mailbox1
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ1
set in CAN_TI1R register).
Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox
1.
Bit 7
ABRQ0: Abort Request for Mailbox0
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 6:4 Reserved, forced by hardware to 0.
Bit 3
TERR0: Transmission Error of Mailbox0
This bit is set when the previous TX failed due to an error.
Bit 2
ALST0: Arbitration Lost for Mailbox0
This bit is set when the previous TX failed due to an arbitration lost.
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ST ST32M103 Series Specifications

General

Brand	ST
Model	ST32M103 Series
Category	Microcontrollers
Language	English