ST ST32M103 Series

To Next Page

To Previous Page

UM0306 Inter-integrated circuit (I2C) interface

355/519

Bit 1

BUSY: Bus Busy

0: No communication on the bus

1: Communication ongoing on the bus

– Set by hardware on detection of SDA or SCL low

– cleared by hardware on detection of a Stop condition.

It indicates a communication in progress on the bus. This information is still

updated when the interface is disabled (PE=0).

Bit 0

MSL: Master/Slave

0: Slave Mode

1: Master Mode

– Set by hardware as soon as the interface is in Master mode (SB=1).

– Cleared by hardware after detecting a Stop condition on the bus or a loss of

arbitration (ARLO=1), or by hardware when PE=0.

www.BDTIC.com/ST

Main Page

Table of Contents2
Documentation Conventions23
List of Abbreviations for Registers23
Memory and Bus Architecture24
System Architecture24
Figure 1. System Architecture24
Memory Organization25
Memory Map26
Figure 2. Memory Map26
Peripheral Memory Map27
Table 1. Register Boundary Addresses27
Embedded SRAM28
Bit Banding29
Embedded Flash Memory29
Table 2. Flash Module Organization30
Boot Configuration32
Table 3. Boot Modes32
Power Control (PWR)33
Power Supplies33
Independent A/D Converter Supply and Reference Voltage33
Figure 3. Power Supply Overview33
Battery Backup34
Voltage Regulator34
Power Supply Supervisor34
Power on Reset (Por)/Power down Reset (PDR)34
Programmable Voltage Detector (PVD)35
Figure 4. Power on Reset/Power down Reset Waveform35
Figure 5. PVD Thresholds35
Low-Power Modes36
Slowing down System Clocks36
Table 4. Low-Power Mode Summary36
Peripheral Clock Gating37
SLEEP Mode37
Table 5. SLEEP-NOW Mode37
STOP Mode38
Table 6. SLEEP-ON-EXIT Mode38
STANDBY Mode39
Table 7. STOP Mode39
Auto-Wake-Up (AWU) from Low-Power Mode40
Table 8. STANDBY Mode40
Power Control Registers41
Power Control Register (PWR_CR)41
Power Control/Status Register (PWR_CSR)43
PWR Register Map44
Table 9. PWR - Register Map and Reset Values44
Reset and Clock Control (RCC)45
Reset45
System Reset45
Power Reset46
Backup Domain Reset46
Clocks46
Figure 6. Reset Circuit46
Figure 7. Clock Tree47
HSE Clock48
Figure 8. HSE/ LSE Clock Sources48
HSI Clock49
Pll49
LSE Clock50
LSI Clock50
System Clock (SYSCLK) Selection50
Clock Security System (CSS)51
RTC Clock51
Watchdog Clock51
Clock-Out Capability51
RCC Register Description52
Clock Control Register (RCC_CR)52
Clock Configuration Register (RCC_CFGR)54
Clock Interrupt Register (RCC_CIR)57
APB2 Peripheral Reset Register (RCC_APB2RSTR)60
APB1 Peripheral Reset Register (RCC_APB1RSTR)62
AHB Peripheral Clock Enable Register (RCC_AHBENR)64
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)65
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)67
Backup Domain Control Register (RCC_BDCR)69
Control/Status Register (RCC_CSR)70
RCC Register Map72
Table 10. RCC - Register Map and Reset Values72
General Purpose and Alternate Function I/O (GPIO and AFIO)73
GPIO Functional Description73
General Purpose I/O (GPIO)74
Table 12. Output Mode Bits74
Figure 9. Basic Structure of an I/O Port Bit74
Atomic Bit Set or Bit Reset75
External Interrupt/Wake-Up Lines75
Alternate Functions (AF)75
Software Remapping of I/O Alternate Functions76
GPIO Locking Mechanism76
Input Configuration76
Figure 10. Input Floating/Pull Up/Pull down Configurations76
Output Configuration77
Alternate Function Configuration77
Figure 11. Output Configuration77
Analog Input Configuration78
Figure 12. Alternate Function Configuration78
Figure 13. High Impedance-Analog Input Configuration79
GPIO Register Description80
Port Configuration Register Low (Gpiox_Crl) (X=A..e80
Port Configuration Register High (Gpiox_Crh) (X=A..e81
Port Input Data Register (Gpiox_Idr) (X=A..e82
Port Output Data Register (Gpiox_Odr) (X=A..e83
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..e84
Port Bit Reset Register (Gpiox_Brr) (X=A..e85
Port Configuration Lock Register (Gpiox_Lckr) (X=A..e86
Alternate Function I/O and Debug Configuration (AFIO)87
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD187
BXCAN Alternate Function Remapping87
JTAG/SWD Alternate Function Remapping87
Table 13. BXCAN Alternate Function Remapping87
Table 14. Debug Interface Signals87
Timer Alternate Function Remapping88
Table 15. Debug Port Mapping88
Table 16. Timer 4 Alternate Function Remapping88
Table 17. Timer 3 Alternate Function Remapping88
USART Alternate Function Remapping89
Table 18. Timer 2 Alternate Function Remapping89
Table 19. Timer 1 Alternate Function Remapping89
Table 20. USART3 Remapping89
I2C 1 Alternate Function Remapping90
SPI 1 Alternate Function Remapping90
Table 21. USART2 Remapping90
Table 22. USART1 Remapping90
Table 23. I2C1 Remapping90
Table 24. SPI1 Remapping90
AFIO Register Description91
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)92
External Interrupt Configuration Register 1 (AFIO_EXTICR1)95
External Interrupt Configuration Register 2 (AFIO_EXTICR2)95
External Interrupt Configuration Register 3 (AFIO_EXTICR3)96
External Interrupt Configuration Register 4 (AFIO_EXTICR4)96
GPIO and AFIO Register Maps97
GPIO Register Map97
AFIO Register Map97
Table 25. GPIO Register Map and Reset Values97
Table 26. AFIO Register Map and Reset Values97
Interrupts and Events98
Nested Vectored Interrupt Controller (NVIC)98
Systick Calibration Value Register98
Interrupt and Exception Vectors98
Table 27. Vector Table98
External Interrupt/Event Controller (EXTI)101
Main Features101
Block Diagram101
Figure 14. External Interrupt/Event Controller Block Diagram101
Wake-Up Event Management102
Functional Description102
External Interrupt/Event Line Mapping103
EXTI Register Description103
Figure 15. External Interrupt/Event GPIO Mapping103
EXTI Register Map107
Table 28. External Interrupt/Event Controller Register Map and Reset Values107
DMA Controller (DMA)108
Introduction108
Main Features108
Functional Description109
DMA Transactions109
Figure 16. DMA Block Diagram109
Arbiter110
DMA Channels110
Error Management111
DMA Request Mapping112
Figure 17. DMA Request Mapping112
DMA Registers113
DMA Interrupt Status Register (DMA_ISR)113
Table 29. Summary of DMA Requests for each Channel113
DMA Interrupt Flag Clear Register (DMA115
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1116
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1117
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1118
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1118
DMA Register Map118
Real-Time Clock (RTC)121
Introduction121
Main Features121
Functional Description121
Overview121
Figure 18. RTC Simplified Block Diagram122
Resetting RTC Registers123
Reading RTC Registers123
Configuring RTC Registers124
Asserting RTC Flags124
Figure 19. RTC Second and Alarm Waveform Example with PR=0003, ALARM=00004124
RTC Register Description125
RTC Control Register High (RTC_CRH)125
Figure 20. RTC Overflow Waveform Example with PR=0003125
RTC Control Register Low (RTC_CRL)126
RTC Prescaler Load Register (RTC_PRLH / RTC_PRLL)128
RTC Prescaler Divider Register (RTC_DIVH / RTC_DIVL)129
RTC Counter Register (RTC_CNTH / RTC_CNTL)130
RTC Alarm Register High (RTC_ALRH / RTC_ALRL)131
RTC Register Map132
Table 31. RTC - Register Map and Reset Values132
Backup Registers (BKP)133
Introduction133
Features133
Tamper Detection133
RTC Calibration134
BKP Register Description134
Backup Data Register X (Bkp_Drx) (X = 1134
RTC Clock Calibration Register (BKP_RTCCR)134
Backup Control Register (BKP_CR)135
Backup Control/Status Register (BKP_CSR)135
BKP Register Map137
Table 32. BKP - Register Map and Reset Values137
Independent Watchdog (IWDG)138
Introduction138
Hardware Watchdog138
Register Access Protection138
Debug Mode138
IWDG Register Description139
Key Register (IWDG_KR)139
Table 33. Watchdog Time-Out Period (with 32 Khz Input Clock)139
Figure 21. Independent Watchdog Block Diagram139
Prescaler Register (IWDG_PR)141
Reload Register (IWDG_RLR)142
Status Register (IWDG_SR)142
IWDG Register Map144
Table 34. IWDG Register Map and Reset Values144
Window Watchdog (WWDG)145
Introduction145
Main Features145
Functional Description145
Figure 22. Watchdog Block Diagram145
How to Program the Watchdog Timeout146
Debug Mode147
Figure 23. Window Watchdog Timing Diagram147
Register Description148
Control Register (WWDG_CR)148
Configuration Register (WWDG_CFR)148
Status Register (WWDG_SR)149
WWDG Register Map150
Table 35. WWDG Register Map and Reset Values150
Advanced Control Timer (TIM1)151
Introduction151
Main Features151
Block Diagram152
Figure 24. Advanced Control Timer (TIM1) Block Diagram152
Functional Description153
Time Base Unit153
Counter Modes154
Figure 25. Counter Timing Diagram with Prescaler Division Change from 1 to 2154
Figure 26. Counter Timing Diagram with Prescaler Division Change from 1 to 4154
Figure 27. Counter Timing Diagram, Internal Clock Divided by 1155
Figure 28. Counter Timing Diagram, Internal Clock Divided by 2155
Figure 29. Counter Timing Diagram, Internal Clock Divided by 4156
Figure 30. Counter Timing Diagram, Internal Clock Divided by N156
Figure 31. Counter Timing Diagram, Update Event When ARPE=0 (TIM1_ARR Not Preloaded)156
Figure 32. Counter Timing Diagram, Update Event When ARPE=1 (TIM1_ARR Preloaded)157
Figure 33. Counter Timing Diagram, Internal Clock Divided by 1158
Figure 34. Counter Timing Diagram, Internal Clock Divided by 2158
Figure 35. Counter Timing Diagram, Internal Clock Divided by 4158
Figure 37. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used159
Figure 38. Counter Timing Diagram, Internal Clock Divided by 1, Tim1_Arr=0X6160
Figure 39. Counter Timing Diagram, Internal Clock Divided by 2160
Figure 40. Counter Timing Diagram, Internal Clock Divided by 4, Tim1_Arr=0X36161
Figure 42. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)161
Repetition Down-Counter162
Figure 43. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)162
Figure 44. Update Rate Examples Depending on Mode and TIM1_RCR Register Settings163
Clock Selection164
Figure 45. Control Circuit in Normal Mode, Internal Clock Divided by 1164
Figure 46. TI2 External Clock Connection Example164
Figure 47. Control Circuit in External Clock Mode 1165
Figure 48. External Trigger Input Block165
Capture/Compare Channels166
Figure 49. Control Circuit in External Clock Mode 2166
Figure 50. Capture/Compare Channel (Example: Channel 1 Input Stage)167
Figure 51. Capture/Compare Channel 1 Main Circuit167
Input Capture Mode168
Figure 52. Output Stage of Capture/Compare Channel (Channel 1 to 3)168
Figure 53. Output Stage of Capture/Compare Channel (Channel 4)168
PWM Input Mode169
Forced Output Mode170
Figure 54. PWM Input Mode Timing170
Output Compare Mode171
PWM Mode172
Figure 55. Output Compare Mode, Toggle on OC1172
Figure 56. Edge-Aligned PWM Waveforms (ARR=8)173
Complementary Outputs and Dead-Time Insertion174
Figure 57. Center-Aligned PWM Waveforms (ARR=8)174
Figure 58. Complementary Output with Dead-Time Insertion175
Figure 59. Dead-Time Waveforms with Delay Greater than the Negative Pulse175
Figure 60. Dead-Time Waveforms with Delay Greater than the Positive Pulse175
Using the Break Function176
Figure 61. Output Behavior in Response to a Break178
Clearing the Ocxref Signal on an External Event179
Figure 62. Clearing TIM1 Ocxref179
6-Step PWM Generation180
Figure 63. 6-Step Generation, COM Example (OSSR=1)180
One Pulse Mode181
Figure 64. Example of One Pulse Mode181
Encoder Interface Mode182
Table 36. Counting Direction Versus Encoder Signals183
Figure 65. Example of Counter Operation in Encoder Interface Mode184
Figure 66. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted184
Timer Input XOR Function185
Interfacing with Hall Sensors185
Figure 67. Example of Hall Sensor Interface186
Timers and External Trigger Synchronization187
Figure 68. Control Circuit in Reset Mode187
Figure 69. Control Circuit in Gated Mode188
Figure 70. Control Circuit in Trigger Mode189
Timer Synchronization190
Debug Mode190
Figure 71. Control Circuit in External Clock Mode 2 + Trigger Mode190
TIM1 Register Description191
Control Register 1 (TIM1_CR1)191
Control Register 2 (TIM1_CR2)193
Slave Mode Control Register (TIM1_SMCR)195
Dma/Interrupt Enable Register (TIM1_DIER)198
Status Register (TIM1_SR)200
Event Generation Register (TIM1_EGR)202
Capture/Compare Mode Register 1 (TIM1_CCMR1)204
Capture/Compare Mode Register 2 (TIM1_CCMR2)208
Capture/Compare Enable Register (TIM1_CCER)209
Table 37. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature211
Counter (TIM1_CNT)212
Prescaler (TIM1_PSC)212
Auto-Reload Register (TIM1_ARR)212
Repetition Counter Register (TIM1_RCR)213
Capture/Compare Register 1 (TIM1_CCR1)213
Capture/Compare Register 2 (TIM1_CCR2)214
Capture/Compare Register 3 (TIM1_CCR3)214
Capture/Compare Register 4 (TIM1_CCR4)215
Break and Dead-Time Register (TIM1_BDTR)216
DMA Control Register (TIM1_DCR)218
DMA Address for Burst Mode (TIM1_DMAR)218
TIM1 Register Map219
Table 38. TIM1 - Register Map and Reset Values219
General Purpose Timer (Timx)221
Introduction221
Main Features221
Block Diagram222
Functional Description222
Time Base Unit222
Figure 72. General Purpose Timer Block Diagram222
Figure 73. Counter Timing Diagram with Prescaler Division Change from 1 to 2223
Counter Modes224
Figure 74. Counter Timing Diagram with Prescaler Division Change from 1 to 4224
Figure 75. Counter Timing Diagram, Internal Clock Divided by 1225
Figure 76. Counter Timing Diagram, Internal Clock Divided by 2225
Figure 77. Counter Timing Diagram, Internal Clock Divided by 4225
Figure 78. Counter Timing Diagram, Internal Clock Divided by N226
Figure 79. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)226
Figure 80. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)227
Figure 81. Counter Timing Diagram, Internal Clock Divided by 1228
Figure 82. Counter Timing Diagram, Internal Clock Divided by 2228
Figure 83. Counter Timing Diagram, Internal Clock Divided by 4228
Figure 84. Counter Timing Diagram, Internal Clock Divided by N229
Figure 85. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used229
Figure 86. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6230
Figure 87. Counter Timing Diagram, Internal Clock Divided by 2230
Figure 88. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36231
Figure 89. Counter Timing Diagram, Internal Clock Divided by N231
Figure 90. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)231
Clock Selection232
Figure 91. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)232
Figure 92. Control Circuit in Normal Mode, Internal Clock Divided by 1233
Figure 93. TI2 External Clock Connection Example233
Figure 94. Control Circuit in External Clock Mode 1234
Figure 95. External Trigger Input Block234
Capture/Compare Channels235
Figure 96. Control Circuit in External Clock Mode 2235
Figure 97. Capture/Compare Channel (Example: Channel 1 Input Stage)235
Input Capture Mode236
Figure 98. Capture/Compare Channel 1 Main Circuit236
Figure 99. Output Stage of Capture/Compare Channel (Channel 1)236
PWM Input Mode237
Forced Output Mode238
Figure 100. PWM Input Mode Timing238
Output Compare Mode239
PWM Mode240
Figure 101. Output Compare Mode, Toggle on OC1240
Figure 102. Edge-Aligned PWM Waveforms (ARR=8)241
One Pulse Mode242
Figure 103. Center-Aligned PWM Waveforms (ARR=8)242
Figure 104. Example of One Pulse Mode243
Clearing the Ocxref Signal on an External Event244
Figure 105. Clearing Timx Ocxref244
Table 39. Counting Direction Versus Encoder Signals245
Figure 106. Example of Counter Operation in Encoder Interface Mode246
Figure 107. Example of Encoder Interface Mode with IC1FP1 Polarity Inverted246
Figure 108. Control Circuit in Reset Mode248
Figure 109. Control Circuit in Gated Mode249
Figure 110. Control Circuit in Trigger Mode250
Figure 111. Control Circuit in External Clock Mode 2 + Trigger Mode251
Figure 112. Master/Slave Timer Example252
Figure 113. Gating Timer 2 with OC1REF of Timer 1253
Figure 114. Gating Timer 2 with ENABLE of Timer 1254
Figure 115. Triggering Timer 2 with UPDATE of Timer 1254
Figure 116. Triggering Timer 2 with ENABLE of Timer 1255
Figure 117. Triggering Timer 1 and 2 with Timer 1 TI1 Input256
Table 40. Output Control Bit for Standard Ocx Channels275
Table 41. Timx - Register Map and Reset Values280
Figure 118. CAN Network Topology283
Figure 119. CAN Block Diagram284
Figure 120. Bxcan Operating Modes284
Figure 121. Bxcan in Silent Mode286
Figure 122. Bxcan in Loop Back Mode287
Figure 123. Bxcan in Combined Mode287
Figure 124. Transmit Mailbox States289
Figure 125. Receive FIFO States290
Figure 126. Filter Bank Scale Configuration - Register Organization292
Figure 127. Example of Filter Numbering293
Figure 128. Filtering Mechanism - Example294
Table 42. Transmit Mailbox Mapping295
Table 43. Receive Mailbox Mapping295
Figure 129. CAN Error State Diagram296
Figure 130. Bit Timing297
Figure 131. CAN Frames298
Figure 132. Event Flags and Interrupt Generation299
Table 44. Bxcan - Register Map and Reset Values324
Figure 133. I2C Bus Protocol329
Figure 134. I2C Block Diagram330
Figure 135. Transfer Sequence Diagram for Slave Transmitter332
Figure 136. Transfer Sequence Diagram for Slave Receiver333
Figure 137. Transfer Sequence Diagram for Master Transmitter336
Figure 138. Transfer Sequence Diagram for Master Receiver337
Table 45. Smbus Vs I2C339
Table 46. I2C Interrupt Requests344
Figure 139. I2C Interrupt Mapping Diagram345
Table 47. I2C Register Map and Reset Values358
Figure 140. SPI Block Diagram360
Figure 141. Single Master/ Single Slave Application361
Figure 142. Hardware/Software Slave Select Management361
Figure 143. Data Clock Timing Diagram363
Table 48. SPI Interrupt Requests369
Table 49. SPI Register Map and Reset Values376
Figure 144. USART Block Diagram381
Figure 145. Word Length Programming382
Figure 146. Configurable Stop Bits384
Table 50. Noise Detection from Sampled Data387
Figure 147. Data Sampling for Noise Detection387
Table 51. Error Calculation for Programmed Baud Rates390
Figure 148. Mute Mode Using Idle Line Detection391
Figure 149. Mute Mode Using Address Mark Detection391
Table 52. Frame Formats392
Figure 150. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)394
Figure 151. Break Detection in LIN Mode Vs Framing Error Detection395
Figure 152. USART Example of Synchronous Transmission396
Figure 153. USART Data Clock Timing Diagram (M=0)396
Figure 154. USART Data Clock Timing Diagram (M=1)397
Figure 155. RX Data Setup/Hold Time397
Figure 156. ISO 7816-3 Asynchronous Protocol398
Figure 157. Parity Error Detection Using the 1.5 Stop Bits399
Figure 158. Irda SIR ENDEC- Block Diagram401
Figure 159. Irda Data Modulation (3/16) -Normal Mode401
Figure 160. Hardware Flow Control between 2 USART403
Figure 161. RTS Flow Control403
Figure 162. CTS Flow Control404
Table 53. USART Interrupt Requests405
Figure 163. USART Interrupt Mapping Diagram405
Table 54. USART Register Map and Reset Values418
Figure 164. USB Peripheral Block Diagram420
Figure 165. Packet Buffer Areas with Examples of Buffer Description Table Locations425
Table 55. Double-Buffering Buffer Flag Definition430
Table 56. Bulk Double-Buffering Memory Buffers Usage430
Table 58. Resume Event Detection433
Table 59. Reception Status Encoding444
Table 60. Endpoint Type Encoding445
Table 61. Endpoint Kind Meaning445
Table 62. Transmission Status Encoding445
Table 63. Definition of Allocated Buffer Memory449
Table 64. USB Register Map and Reset Values450
Figure 166. Single ADC Block Diagram452
Figure 167. Timing Diagram455
Figure 168. Analog Watchdog Guarded Area455
Table 66. Analog Watchdog Channel Selection456
Figure 169. Injected Conversion Latency457
Figure 170. Calibration Timing Diagram459
Figure 171. Right Alignment of Data460
Figure 172. Left Alignment of Data460
Table 67. External Trigger for Regular Channels461
Table 68. External Trigger for Injected Channels461
Figure 173. Dual ADC Block Diagram463
Figure 174. Injected Simultaneous Mode on 4 Channels464
Figure 175. Regular Simultaneous Mode on 16 Channels464
Figure 176. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode465
Figure 177. Slow Interleaved Mode on 1 Channel466
Figure 178. Alternate Trigger: Injected Channel Group of each Adcl466
Figure 179. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model467
Figure 180. Alternate + Regular Simultaneous467
Figure 181. Case of Trigger Occurring During Injected Conversion468
Figure 182. Interleaved Single Channel with Injected Sequence CH11, CH12468
Figure 183. Temperature Sensor and VREFINT Channel Block Diagram469
Table 69. ADC Interrupts470
Table 70. ADC - Register Map and Reset Values485
Figure 184. Block Diagram of Stm32F10X-Level and Cortex-M3-Level Debug Support487
Figure 185. JTAG TAP Connections493
Table 71. JTAG Debug Port Data Registers494
Table 72. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]495
Table 73. Packet Request (8-Bits)496
Table 74. ACK Response (3 Bits)497
Table 75. DATA Transfer (33 Bits)497
Table 76. SW-DP Registers498
Table 77. Main ITM Registers502
Table 78. Important TPIU Registers512
Table 79. DBG - Register Map and Reset Values513
Table 80. Document Revision History514

ST ST32M103 Series - Page 355

Table of Contents

Related product manuals