UM0306 Inter-integrated circuit (I2C) interface
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15.6.9 TRISE Register (I2C_TRISE)
Address offset: 20h
Reset Value: 0002h
151413121110987 654321 0
Reserved TRISE[5:0]
rw rw rw rw rw rw
Bits 15:6 Reserved, forced by hardware to 0.
Bits 5:0
TRISE[5:0]: Maximum Rise Time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I
2
C
bus specification, incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 08h and t
CK
=
125 ns therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part,
in order to respect the t
HIGH
parameter.
Note:
TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
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