UM0306 Analog/digital converter (ADC)
473/519
Bits 15:13
DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to
be converted in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
.......
111: 8 channels
Bit 12
JDISCEN: Discontinuous mode on injected channels
This bit set and cleared by software to enable/disable discontinuous mode on
injected group channels
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Bit 11
DISCEN: Discontinuous mode on regular channels
This bit set and cleared by software to enable/disable Discontinuous mode on
regular channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10
JAUTO: Automatic Injected Group conversion
This bit set and cleared by software to enable/disable automatic injected group
conversion after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9
AWDSGL: Enable the watchdog on a single channel in scan mode
This bit set and cleared by software to enable/disable the analog watchdog on
the channel identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8
SCAN: Scan mode
This bit is set and cleared by software to enable/disable Scan mode. In Scan
mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers
are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC or JEOC interrupt is generated only on the end of conversion of
the last channel if the corresponding EOCIE or JEOCIE bit is set
Bit 7
JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion
interrupt for injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Bit 6
AWDIE: Analog Watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog
interrupt. In Scan mode if the watchdog thresholds are crossed, scan is
aborted only if this bit is enabled.
0: Analog Watchdog interrupt disabled
1: Analog Watchdog interrupt enabled
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