Analog/digital converter (ADC) UM0306
474/519
19.13.3 ADC control register 2 (ADC_CR2)
Address offset: 08h
Reset value: 0000 0000h
Bit 5
EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the End of Conversion
interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0
AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to
be guarded by the Analog Watchdog.
00000: Channel ADC_IN0
00001: Channel ADC_IN1
....
01111: Channel ADC_IN15
10000: Channel ADC_IN16 Temperature sensor
10001: Channel ADC_IN17 V
REFINT
Other values reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TS
VREFE
SW
START
SW
STARTJ
EXT
TRIG
EXTSEL[2:0] Res.
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTT
RIG
JEXTSEL[2:0] ALIGN Reserved DMA Reserved
RST
CAL
CAL CONT ADON
rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept cleared.
Bit 23
TSVREFE: Temperature Sensor and V
REFINT
Enable
This bit is set and cleared by software to enable/disable the temperature
sensor and V
REFINT
channel. In devices with dual ADCs this bit is present only
in ADC1.
0: Temperature sensor and V
REFINT
channel disabled
1: Temperature sensor and V
REFINT
channel enabled
Bit 22
SWSTART: Start Conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon
as conversion starts. It starts a conversion of a a group of regular channels if
SWSTART is selected as trigger event by the EXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of regular channels
To Next Page
Loading...
Need help?
General
