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ST STM32F31xx User Manual

ST STM32F31xx
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Reset and clock control (RCC)
UM1581
332/584
DocID023800 Rev 1
18.2.8.12 RCC_APB1PeriphClockCmd
Function Name
void RCC_APB1PeriphClockCmd ( uint32_t RCC_APB1Periph,
FunctionalState NewState)
Function Description
Enables or disables the Low Speed APB (APB1) peripheral clock.
Parameters
ï‚· RCC_APB1Periph : specifies the APB1 peripheral to gates
its clock. This parameter can be any combination of the
following values:
 RCC_APB1Periph_TIM2 :
 RCC_APB1Periph_TIM3 :
 RCC_APB1Periph_TIM4 :
 RCC_APB1Periph_TIM6 :
 RCC_APB1Periph_TIM7 :
 RCC_APB1Periph_WWDG :
 RCC_APB1Periph_SPI2 :
 RCC_APB1Periph_SPI3 :
 RCC_APB1Periph_USART2 :
 RCC_APB1Periph_USART3 :
 RCC_APB1Periph_UART4 :
 RCC_APB1Periph_UART5 :
 RCC_APB1Periph_I2C1 :
 RCC_APB1Periph_I2C2 :
 RCC_APB1Periph_USB :
 RCC_APB1Periph_CAN1 :
 RCC_APB1Periph_PWR :
 RCC_APB1Periph_DAC :
ï‚· NewState : new state of the specified peripheral clock. This
parameter can be: ENABLE or DISABLE.
Return values
ï‚· None.
Notes
ï‚· After reset, the peripheral clock (used for registers read/write
access) is disabled and the application software has to enable
this clock before using it.
18.2.8.13 RCC_AHBPeriphResetCmd
Function Name
void RCC_AHBPeriphResetCmd ( uint32_t RCC_AHBPeriph,
FunctionalState NewState)
Function Description
Forces or releases AHB peripheral reset.

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ST STM32F31xx Specifications

General IconGeneral
BrandST
ModelSTM32F31xx
CategoryMicrocontrollers
LanguageEnglish

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