Basic
Applications-2230
Operators
ANTI-ALIASING.
In
the event that
an
alias
is
suspected, three things may
be
done to determine whether
the display
is
of
an
alias. The first
is
to switch back to
NON
STORE mode to determine if the input signal
is
higher
in
frequency than the apparent signal being
displayed
(see
Figure 6-13B). Ensure that this display
is
being triggered
as
indicated
by
the TRIG'D LED being
illuminated. The second
is
to use either the ACCPEAK or
the PEAKDET storage modes (PEAKDET
is
the default
mode for SEC/DIV settings from 5 s per division to
20
µs
per division), which hold the maximum,
and
minimum
points being acquired. PEAKDET storage mode holds the
maximum
and
minimum points acquired
in
a single trigger
cycle,
and
ACCPEAK accumulates the maximum
and
minimum points acquired over many trigger cycles. Since
the maximum
and
minimum points
of
the alias waveform
do
not occur at exactly the same point
in
relation to the
trigger each time, the display soon acquires maximum
and
minimum amplitude levels
in
every storage address and
the top
and
bottom of the alias display become flat lines
( see Figure 6-13C).
6-14
(A) POSSIBLE ALIAS SIGNAL
IN
STORE MODE.
I
I-
r
I-
. . .
.
I-
.
I-
I
(8)
NON STORE DISPLAY.
90--+--+-----t--+---+----+----+---+---+---<
I-
(C) ALIAS SIGNAL DISPLAY
IN
ACCPEAK
STORE MODE.
Figure 6-13. Anti-aliasing.
4998-26
Third, if
an
alias is detected, the SEC/DIV switch may
be
set for a faster sweep rate
so
that the number
of
sam-
ples per cycle of the input signal
is
increased. However, at
sweep speeds
of
2
µS
per division
and
faster, the sampling
rate is not increased;
and
if
an
alias signal is still present
at 5
µS
per division, the frequency limit of the digital
circuitry has
been
exceeded for non-repetitive signals.
When the SEC/DIV switch is set for sweep speeds faster
than 5 µs/div, Repetitive Store acquisition mode and
AVERAGE are selected.
On
repetitive signals, the random
phase between successive triggers and the time-base
clock suppress aliased waveform displays as a result
of
the increased effective sample rate.
GLITCH CATCHING. Pulses that are present for a very
st1ort
time duration during the viewing of longer pulse
duration signals, such
as
a logic pulse train, may not be
visible at the sweep speed
in
use (see Figure 6-14A).
In
digital logic circuitry, a small switching transient (glitch)
may cross the logic threshold level
and
cause
an
error.
Setting up the instrument to trigger
on
the error event
should position the storage window to acquire the pulse
train that contains the glitch.
90
I-
~
10
(A) NON STORE (GLITCH NOT VISIBLE).
90--+---+----+--+--+---t--------+--+---+----t
'
IQ
--+---+----+--+--+---f------+--+---+------1
(8)
ACCPEAK STORE MODE (GLITCH DISPLAYED).
4998-27
Figure 6-14. Glitch display, ACCPEAK Store mode.
To catch a glitch, first select PRETRIG ACQUISITION
mode. This will acquire 7 /8 of a waveform occurring before
the trigger. Select ACCPEAK mode using the Menu. This
will acquire the waveform maximum
and
minimum points
over a selected number of sweeps. The location of the
glitch will
be
displayed
in
the accumulative envelope
display
(see
Figure 6-14B).
--
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