Townshend Computer Tools DAT-Link - Page 137

C.2 Sync 133
Table C.2: Sync Pinout
Pin Number Connection(s) Direction
1 +5V From DAT-Link +
2 DSPIN To DAT-Link +
3 DSPOUT From DAT-Link +
4 READY Bidirectional
5 MCK Bidirectional
6 SCK Bidirectional
7 FSYNC Bidirectional
8 Ground
in Section 10.3. FSYNC isaword clock with a high level during the left sample and a
low level during the right sample. SCK is a serial bit clock at 64 times the sampling
rate and MCK is a master clock with a frequency of 256 or 384 times the sampling
rate. For sampling rates of 48,000 or 44,100 samples/second, the 256 divider is
used while the 384 divider is used for 32,000 samples/second. All three of these
clo cks must be provided for the DAT-Link + to use an external clo ck for
playback.