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Xerox 560 Reference Manual

Xerox 560
206 pages
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BIR
BRANCH
ON
INCREMENTING
REGISTER
(Word
index
alignment)
BRANCH
ON
INCREMENTING
REGISTER
computes
the
effective
virtual
address and
then
increments
the
contents
of
general
register
R
by
1.
If
the
result is a
negative
value,
the
branch
condition
is
satisfied
and
instruction
execution
then
proceeds
with
the
instruction
pointed
to
by the
effec-
tive
address
of
the
BIR
instruction.
However,
if
the
result
is
zero
or
a
positive
va
lue,
the
branch
condition
is not
sat-
isfied
and
instruction
execution
proceeds
with
the
next
in-
struction
in normal
sequence.
Affected:
(R),(IA)
(R)
+ 1 - R
If
(R)O
=
1,
EVA
15
_
31
-IA
If
(R)O
=
0,
IA
not
affected
If
the
branch
condition
is
satisfied
and if
the
effective
ad-
dress
of
BIR
is
either
unavailable
to
the
program (slave
or
master-protected
mode) for instruction
access
or
is
non-
existent,
the
basi c processor aborts
execution
of
the
BIR
instruction
and
traps
to
location
X'40'.
In
this
case,
the
instruction
address stored by
the
XPSD
instruction
in
loca-
tion
X'40'
is
the
virtual
address
of
the
aborted
BIR
instruc-
tion.
If
the
basic
processor traps
because
of
instruction
access
protection,
register
R will
contain
the
value
that
existed
just
before
the
BIR
execution
(i.e.,
updated
instruc-
tion
address).
If
a memory
parity
error
occurs
due
to
the
accessing
of
the
instruction
to
which
the
program is
branch-
ing,
the
basic
processor aborts
execution
of
the
BIR
and
traps
to
location
X'4C'
with
register
R
unchanged.
BDR
BRANCH
ON
DECREMENTING
REGISTER
(Word index
alignment)
BRANCH
ON
DECREMENTING
REGISTER
computes
the
effective
virtual
address
and
then
decrements
the
contents
of
general
register
R by 1.
If
the
result
is a positive
value,
the
branch
condition
is
satisfied
and
instruction
execution
then
proceeds
with
the
instruction
pointed
to
by
the
effec-
tive
address
of
the
BDR
instruction.
However, if
the
result
is
zero
or
a
negative
value,
the
branch
condition
is
unsatis-
fied
and
instruction
execution
proceeds
with
the
next
in-
struction
in normal
sequence.
Affected:
(R), (IA)
(R)
- 1 - R
If
(R)O
= 0
and
(R)1-31 j
0,
EVA
15
_
31
-
IA
If
(R)O
= 1
and
(R)
=
0,
IA
not
affected
108
Execute/Branch
Instructions
If
the
effective
address
of
BDR
is
unavailable
to
the
program
(slave
or
master-protected
mode) for instruction
access
and
the
branch
condition
is
satisfied,
or
if
the
effective
address
of
BDR
is
nonexistent,
the
basi c processor aborts
execution
of
the
BDR
instruction and traps to
location
X'40'.
In
this
case,
the
instruction address stored by
the
XPSD
instruction
in
location
X'40'
is
the
virtual
address
of
the
aborted
BDR
instruction.
If
the
basi c processor traps
because
of
instruc-
tion
access
protection,
register
Rwill
contain
the
value
that
existed
just before
the
BDR
instruction.
If
a memory
parity
error
occurs
due
to
the
accessing
of
the
instruction
to
whi ch
the
program
is
branching,
the
basic
processor aborts
execu-
tion
of
the
BDR
and traps to
location
X'4C
r with
register
R
unchanged.
BAL
BRANCH
AND
LINK
(Word index
alignment)
BRANCH
AND
LINK determines
the
effective
virtual
ad-
dress,
loads
the
updated
instruction address (the
virtual
ad-
dress
of
the
next
instruction
in
normal
sequence
after
the
BAL
instruction)
into
bit
positions 15-31
of
general
regis-
ter
R,
clears
bit
positions
0-14
of
register
R
to
O's
and
then
replaces
the
updated
instruction address with
the
effective
virtual
address. Instruction
execution
proceeds with
the
instruction
pointed
to
by
the
effective
address
of
the
BAL
instruction.
The
BAL
instruction
in
real
extended
addressing will store
the
full address
of
the
next
instruction
in
the
specified
R
register.
Positions
0-9
of
the
specified
register
will be
set
equal
to
zero.
Affected:
(R),
(IA)
If
the
effective
address
of
BAL
is
unavailable
to
the
program
(slave
or
master-protected
mode) for instruction
access
and
the
branch
condition
is
satisfied,
or
if
the
effective
address
of
BAL
is
nonexistent,
the
basic
processor
aborts
execution
ofthe
BAL
instruction
and
traps
to
location
X'40'
(nonallowed
operation
trap).
In
this
case,
the
instruction address stored
by
the
XPSD instruction in
location
X'40'
is
the
virtual
ad-
dress
of
the
aborted
SAL
instruction.
If
the
basic
processor
traps
because
of
instruction
access
protection,
register R will
contain
the
updated
instruction address.
If
a memory
parity
error
occurs
due
to
the
accessing
of
the
instruction
to
which
the
program
is
branching,
the
basic
processor aborts
execu-
tion
of
the
BA
L and traps to
location
X'4C
r with
register
R
changed
to
the
updated
instruction address.

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Xerox 560 Specifications

General IconGeneral
Print Resolution2400 x 2400 dpi
Monthly Duty CycleUp to 300, 000 pages
Duplex PrintingStandard
Operating System CompatibilityWindows, Mac OS, Linux
ConnectivityEthernet, USB
Paper SizeUp to 13 x 19.2 inches
TypeMultifunction Printer

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