Xilinx KCU116 - Page 37

KCU116 Board User Guide 37
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Table 3-7 lists the GTY Banks 224 and 225 interface connections between FPGA U1 and
8-lane PCIe connector P1.
Table3‐7: KCU116 FPGA U1 GTY Banks 224 and 225 Connections to PCIe Connector P1
Transceiver
Bank
FPGA
(U1) Pin
FPGA (U1) Pin Name
Schematic Net
Name
Connected
Pin
Connected
Pin Name
Connected
Device
GTY Bank
224
AFY MGTYTXP0_224 PCIE_TX7_P
(1)
A47 PERp7
PCIe Edge
Connector P1
AF6 MGTYTXN0_224 PCIE_TX7_N
(1)
A48 PERn7
AF2 MGTYRXP0_224 PCIE_RX7_P B45 PETp7
AF1 MGTYRXN0_224 PCIE_RX7_N B46 PETn7
AE9 MGTYTXP1_224 PCIE_TX6_P
(1)
A43 PERp6
AE8 MGTYTXN1_224 PCIE_TX6_N
(1)
A44 PERn6
AE4 MGTYRXP1_224 PCIE_RX6_P B41 PETp6
AE3 MGTYRXN1_224 PCIE_RX6_N B42 PETn6
AD7 MGTYTXP2_224 PCIE_TX5_P
(1)
A39 PERp5
AD6 MGTYTXN2_224 PCIE_TX5_N
(1)
A40 PERn5
AD2 MGTYRXP2_224 PCIE_RX5_P B37 PETp5
AD1 MGTYRXN2_224 PCIE_RX5_N B38 PETn5
AC5 MGTYTXP3_224 PCIE_TX4_P
(1)
A35 PERp4
AC4 MGTYTXN3_224 PCIE_TX4_N
(1)
A36 PERn4
AB2 MGTYRXP3_224 PCIE_RX4_P B33 PETp4
AB1 MGTYRXN3_224 PCIE_RX4_N B34 PETn4
ABY MGTREFCLK0P_224 NC NA NA
AB6 MGTREFCLK0N_224 NC NA NA
Y7 MGTREFCLK1P_224 NC NA NA
Y6 MGTREFCLK1N_224 NC NA NA
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