Zynq-7000 PCB Design Guide www.xilinx.com 27
UG933 (v1.8) November 7, 2014
Chapter 3: Power Distribution System
• Ceramic chip capacitors with a lower ESR, generally have a very narrow effective
frequency band.
An ideal capacitor only has a capacitive characteristic, whereas real non-ideal capacitors
also have a parasitic inductance (ESL) and a parasitic resistance (ESR). These parasitics work
in series to form an RLC circuit (Figure 3-4). The RLC circuit’s resonant frequency is the
capacitor’s self-resonant frequency.
To determine the RLC circuit’s resonant frequency, use Equation 3-1:
Equation 3-1
Another method of determining the self-resonant frequency is to find the minimum point in
the impedance curve of the equivalent RLC circuit. The impedance curve can be computed
or generated in SPICE using a frequency sweep. See the Simulation Methods section for
other ways to compute an impedance curve.
It is important to distinguish between the capacitor's self-resonant frequency and the
mounted capacitor’s effective resonant frequency when the capacitor is part of the system,
F
RIS
. This corresponds to the resonant frequency of the capacitor with its parasitic
inductance, plus the inductance of the vias, planes, and connecting traces between the
capacitor and the AP SoC.
The capacitor’s self-resonant frequency, F
RSELF
, (capacitor data sheet value) is much higher
than its effective mounted resonant frequency in the system, F
RIS
. Because the mounted
capacitor's performance is most important, the mounted resonant frequency is used when
evaluating a capacitor as part of the greater PDS.
Mounted parasitic inductance is a combination of the capacitor's own parasitic inductance
and the inductance of: PCB lands, connecting traces, vias, and power planes. Vias traverse a
full PCB stackup to the device when capacitors are mounted on the PCB backside. For a
board with a finished thickness of 1.524 mm (60 mils), these vias contribute approximately
300 pH to 1,500 pH, (the capacitor’s mounting parasitic inductance, L
MOUNT
) depending on
the spacing between vias. Wider-spaced vias and vias in thicker boards have higher
inductance.
To determine the capacitor’s total parasitic inductance in the system, L
IS
, the capacitor's
parasitic inductance, L
SELF
, is added to the mounting’s parasitic inductance, L
MOUNT
:
L
IS
= L
SELF
+ L
MOUNT
Equation 3-2
For example, using X7R Ceramic Chip capacitor in 0402 body size:
C = 0.01 μF (selected by user)
L
SELF
= 0.9 nH (capacitor data sheet parameter)
F
RSELF
= 53 MHz (capacitor data sheet parameter)
F
1
2π LC
-------------------=
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