YASKAWA SGDA series User Manual

3.2Setting User Constants According to Host Controller
73
For position control (SGDA-
jjj
P) only.
Selects the pulse form of error counter clear signal CLR (1CN-5).
Setting Meaning
0
Clears the error counter when the CLR
signal is set at high level. Error pulses
do not accumulate while the signal
remains at high level.
Cleared state
1
Clears the error counter only once when
the rising edge of the CLR signal rises.
Cleared only once at this point
3.2.3 Using Encoder Output
1) Encoder output signals divided inside the Servopack can be output externally. These
signals can be used to form a position control loop in the host controller.
Servomotor
encoder
Servopack
Frequency
dividing
circuit
Host
controller
This output is
explained here.
Phase A
Phase B
Phase C
TERMS
Divided (or dividing)
“Dividing” means converting an input pulse train from the encoder mounted on the motor
according to the preset pulse density and outputting the converted pulse. The unit is pulses
per revolution.
3

YASKAWA SGDA series Specifications

General

Brand	YASKAWA
Model	SGDA series
Category	Servo Drives
Language	English