Ametek UPLC-II - Page 114

Page 5–22
UPLC-II™ System Manual
Options
Trip Test Enabled
or Disabled
Receiver Logic
LR Pre-Trip Delay* 0 to 30 ms DTT Pre-Trip Delay* 0 to 30 ms
LR Trip Hold 0 to 100 ms DTT Trip Hold 0 to 100 ms
LR Guard Hold 0 to 100 ms DTT Guard Hold 0 to 100 ms
LR Unblock Timer 0 to 500 ms
LR Unblock Delay 0 to 100 ms
LR Guard Before None, GBT or DTT Guard Before None, GBT or
Trip GBT w/Override Trip GBT w/Override
Table 5–10. Logic Settings for 3-Frequency
(FSK Mode)
Receiver Logic
Cmd A Pre-Trip Delay* 0 - 30 ms Cmd B Pre-Trip Delay* 0 - 30 ms
Cmd A Trip Hold 0 - 100 ms Cmd B Trip Hold 0 - 100 ms
Cmd A Guard Hold 0 - 100 ms Cmd B Guard Hold 0 - 100 ms
Cmd A Unblock Timer 0 - 500 ms Cmd B Unblock Time 0 - 500ms
Cmd A Unblock Delay 0 - 100 ms Cmd B Unblock Delay 0 - 100ms
Cmd A Guard Before None, GBT or Cmd B Guard Before None, GBT or
Trip GBT w/Override Trip GBT w/Override
Table 5–11. Logic Settings for 4-Frequency
(FSK Mode)
* For every msec of pre-trip delay you add, the security, against noise causing a false trip, increases exponentially.
UB&POTT: A min of 2-4 msec is recommended.
DTT:The time delay should be as long as the critical stability of your system can tolerate, at least 10 msec min.
LR = Line Relaying