Ametek UPLC-II - Page 48

Page 3–2
UPLC-II™ System Manual
Breaker 1 Channel
Start Fault Detectors (S
1
)
Breaker 2 Channel
Start Fault Detectors (S
2
)
Breaker 1 Trip
Fault Detector (P
1
)
Breaker 2 Trip Fault Detector (P
2
)
Protected Line
G
H
F
I
F
E
Power Line Carrier
C
hannel
1 2
RR
P
CS
Channel
Signal
Receiver
RR
Trip
Coil
52a
Stop Channel
Signal if
Initiated
Locally
Initiate
Channel
Signal
S
Pick-up
Approximately
13–16 Ms
CS
Stop Channel Signal if
Initiated Locally
Timer
P
Trip
S From
Remote Terminal
Via Channel
Note: (P) Operation or (S) Signal
Provides an Input 1 on Circuit.
AND
X
O
S Initiate Channel Signal
X – Nominally Between 6–16 Ms
Figure 3–1a. – Basic Elements for directional-comparison blocking systems
Figure 3–1c. – Solid State Logic (per Terminal)
Figure 3–1b. – Contact Logic (per Terminal)