ARM Cortex-A9 MBIST User Manual

Introduction
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 1-3
Restricted Access Non-Confidential
1.2 MBIST controller interface
Figure 1-2 shows the nonprotein configuration of the MBIST controller interface to the
Automated Test Equipment (ATE) and to the MBIST interface of the Cortex-A9
processor.
Figure 1-2 MBIST controller wiring diagram
Figure 1-3 on page 1-4 shows the traditional method of accessing RAMs for MBIST.
MBISTDATAIN
nRESET
MBISTENABLE
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTRESULT[5:0]
nRESET
CLK CLK
MBISTDOUTDATA[255:0]
nRESET
MBISTENABLE
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTDATAIN
MBISTRESULT[5:0]
MBISTARRAY[19:0]
MBISTBE[25:0]
MBISTADDR[10:0]
MBISTINDATA[63:0]
MBISTARRAY[19:0]
MBISTBE[25:0]
MBISTADDR[10:0]
MBISTINDATA[63:0]
MBISTENABLE
MBISTDOUTDATA[255:0]
CLK
nRESET
Automated Test
Equipment (ATE)
MBIST controller Cortex-A9/A9MP
MBISTWRITEEN MBISTWRITEEN

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST