ARM Cortex-A9 MBIST - Table 3-10 Columnwidth Field Encoding; Table 3-11 Cachesize Field Encoding

MBIST Instruction Register
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Table 3-10 shows the supported column widths along with the number of LSB address
bits used for each and the MBIR encodings required to select them.
3.2.9 CacheSize field, MBIR[1:0]
The CacheSize field specifies the size of the cache in your implementation of the
module. Table 3-11 shows the supported cache sizes.
Table 3-10 ColumnWidth field encoding
ColumnWidth MBIR[3:2] Number of columns Number of address bits
b00 4 2
b01 8 3
b10 16 4
b11 32 5
Table 3-11 CacheSize field encoding
CacheSize MBIR[1:0] Cache size
b00 16KB
b10 32KB
b11 64KB
b01
Reserved
a
a. Mapped internally to 16KB