ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 3-13
Restricted Access Non-Confidential
Table 3-10 shows the supported column widths along with the number of LSB address
bits used for each and the MBIR encodings required to select them.
3.2.9 CacheSize field, MBIR[1:0]
The CacheSize field specifies the size of the cache in your implementation of the
module. Table 3-11 shows the supported cache sizes.
Table 3-10 ColumnWidth field encoding
ColumnWidth MBIR[3:2] Number of columns Number of address bits
b00 4 2
b01 8 3
b10 16 4
b11 32 5
Table 3-11 CacheSize field encoding
CacheSize MBIR[1:0] Cache size
b00 16KB
b10 32KB
b11 64KB
b01
Reserved
a
a. Mapped internally to 16KB

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST