ARM Cortex-A9 MBIST User Manual

Introduction
1-6 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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The MBIST controller accesses memory through the MBIST interface of the Cortex-A9
processor. Table 1-1 lists the Cortex-A9 processor MBIST interface signals.
Note
The interface of the MBIST controller communicates with both the ATE and the MBIST
interface of the Cortex-A9 processor. See Appendix A Signal Descriptions for
descriptions of the MBIST controller interface signals. See the Cortex-A9 Processor
Technical Reference Manual for more information about the MBIST interface.
Table 1-1 Cortex-A9 processor MBIST interface signals
Name Type Description
nRESET Input Global active LOW reset signal.
CLK Input Active HIGH clock signal. This clock drives the Cortex-A9 processor logic.
MBISTOUTDATA[255:0] Output Data out bus from all cache RAM blocks.
MBISTENABLE Input Select signal for cache RAM array. This signal is the select input to the
multiplexors that access the cache RAM arrays for test. When asserted,
MBISTENABLE takes priority over all other select inputs to the multiplexors.
MBISTARRAY[19:0] Input One-hot chip enables to select the RAM arrays for test.
MBISTBE[25:0] Input Global write enable signal for all RAM arrays.
MBISTWRITEEN Input Global write enable.
MBISTADDR[10:0] Input Address signal for cache RAM array.
MBISTINDATA[63:0] Input Data bus to the RAM arrays. Not all RAM arrays use the full data width.

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST