ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
3-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
Restricted Access
3.1 About the MBIST instruction register
The MBIST executes loaded instructions stored in the MBIR. The MBIR is 58 bits wide
and divided in a control unit part of 18 bits and a dispatch unit part of 40 bits.
The MBIR is loaded through serial port MBISTDATAIN of the control unit when
MBISTSHIFT is asserted. When MBISTSHIFT is asserted again, the control unit
passes MBISTDATAIN serially to the dispatch unit through its MBISTTX[3] port.
Figure 3-1 shows the control unit part of the MBIR.
Figure 3-1 MBIST instruction register control unit
The control unit contains the following fields:
Pattern Specifies the test algorithm.
Control Specifies MBIST mode of operation and sticky or nonsticky fail
flag.
Write latency Specifies the number of cycles to enable a RAM write.
Read latency Specifies the number of cycles to enable a RAM read.
Figure 3-2 shows the dispatch unit part of the MBIR.
Figure 3-2 MBIST instruction register dispatch unit
The dispatch unit contains the following fields:
CPU On Controls the data comparison for the CPUs under test.
Pattern
17 12 11 6 5 3 2 0
Control
(57) (52) (51) (46) (45) (43) (42) (40)
Write Latency
Read Latency
31 28 27 24 23 4 3 1 039 36 35 32
CPU On ArrayEnables
2
MaxXAddr
MaxYAddr
DataWord
CacheSize
ColumnWidth

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST