MBIST Instruction Register
3-4 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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3.2 Field descriptions
The following sections describe the MBIR fields:
• Pattern field, MBIR[57:52]
• Control field, MBIR[51:46] on page 3-7
• Read Latency and Write Latency fields, MBIR[42:40] and MBIR[45:43] on
page 3-7
• CPU On field, MBIR[39:36] on page 3-8
• MaxXAddr and MaxYAddr fields, MBIR[35:32] and MBIR[31:28] on page 3-9
• DataWord field, MBIR[27:24] on page 3-11
• ArrayEnables field, MBIR[23:4] on page 3-11
• ColumnWidth field, MBIR[3:2] on page 3-12
• CacheSize field, MBIR[1:0] on page 3-13.
3.2.1 Pattern field, MBIR[57:52]
The MBIST controller is supplied with industry-standard pattern algorithms and a
bit-line stress algorithm. You can group algorithms together to create a specific memory
test methodology for your product.
Table 3-1 describes the supported algorithms, and Pattern specification on page 3-5
describes their use. The N values in the table indicate the number of RAM accesses per
address location and give an indication of the test time when using that algorithm.
Table 3-1 Pattern field encoding
Pattern
MBIR[57:52] Algorithm name N Description
b000000 Write Solids 1N Write a solid pattern to memory
b000001 Read Solids 1N Read a solid pattern from memory
b000010 Write Checkerboard 1N Write a checkerboard pattern to memory
b000011 Read Checkerboard 1N Read a checkerboard pattern from memory
b000100 March C+ (x-fast) 14N March C+ algorithm, incrementing X-address first
b001011 March C+ (y-fast) 14N March C+ algorithm, incrementing Y-address first
b000101 Fail Pattern 6N Tests memory failure detection capability
b000110 Read Write March (x-fast) 6N Read write march pattern, incrementing X-address first
b000111 Read Write March (y-fast) 6N Read write march pattern incrementing Y-address first
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