Functional Description
2-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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2.1 Functional overview
This section describes the interface between the MBIST controller and the RAMs that
the MBIST controller tests:
• MBIST controller interface
• MBISTINDATA and MBISTOUTDATA mapping on page 2-4
• MBIST controller implementation on page 2-10.
2.1.1 MBIST controller interface
The MBIST controller has one MBIST port, see Appendix A Signal Descriptions. Only
one set of RAM is accessed by the MBIST controller at any time.
You can use the MBIST controller for testing the Cortex-A9 processor compiled RAMs.
You can also choose to design your own MBIST controller.
For the MBIST to run correctly on the Cortex-A9 processor if the dormant/power off
wrappers are implemented, you have to set the signals on the Cortex-A9 processor
interface as shown in Table 2-1:
Table 2-2 shows the interfaces between the MBIST controller and the RAMs that
MBIST tests.
Table 2-1 Cortex-A9 signal settings for MBIST
Signal name Setting
CPURAMCLAMP[3:0] 4’b0000
CPUCLAMP[3:0] 4’b0000
RVALIDM1 1'b0
SCURAMCLAMP 1’b0
Table 2-2 RAM arrays and MBIST controller interfaces
RAM Name
MBISTARRAY
bit
MBISTINDATA
bits
MBISTBE
bits
MBISTOUTDATA
bits
Max
address
bits
SCU tag RAM way 3 [19] [22:0] [22:0] [54:32] [8:0]
SCU tag RAM way 2 [19] [22:0] [22:0] [22:0] [8:0]
SCU tag RAM way 1 [18] [22:0] [22:0] [54:32] [8:0]
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