ARM Cortex-A9 MBIST User Manual

Functional Description
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-3
Restricted Access Non-Confidential
SCU tag RAM way 0 [18] [22:0] [22:0] [22:0] [8:0]
Douter RAM [17] [11:0] [11:0] [11:0] [8:0]
Data data RAM way 3
(arrays 3,7)
[16] [63:0] [7:0] [63:0] [10:0]
Data data RAM way 2
(arrays 2,6)
[15] [63:0] [7:0] [63:0] [10:0]
Data data RAM way 1
(arrays 1,5)
[14] [63:0] [7:0] [63:0] [10:0]
Data data RAM way 0
(arrays 0,4)
[13] [63:0] [7:0] [63:0] [10:0]
Data tag RAM array 3 [12] [25:0] [25:0] [57:32] [8:0]
Data tag RAM array 2 [12] [25:0] [25:0] [25:0] [8:0]
Data tag RAM array 1 [11] [25:0] [25:0] [57:32] [8:0]
Data tag RAM array 0 [11] [25:0] [25:0] [25:0] [8:0]
TLB RAM array 1 [10] [60:0] - [60:0] [5:0]
TLB RAM array 0 [9] [60:0] - [60:0] [5:0]
Global History
Buffer arrays 0,1,2,3
[8] [15:0] [15:0] [15:0] [8:0]
Instruction data RAM
array 7 (way 3 high)
[7] [63:32] - [63:32] [10:0]
Instruction data RAM
array 6 (way 3 low)
[7] [31:0] - [31:0] [10:0]
Instruction data RAM
array 5 (way 2 high)
[6] [63:32] - [63:32] [10:0]
Instruction data RAM
array 4 (way 2 low)
[6] [31:0] - [31:0] [10:0]
Instruction data RAM
array 3 (way 1 high)
[5] [63:32] - [63:32] [10:0]
Table 2-2 RAM arrays and MBIST controller interfaces (continued)
RAM Name
MBISTARRAY
bit
MBISTINDATA
bits
MBISTBE
bits
MBISTOUTDATA
bits
Max
address
bits

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST