ARM Cortex-A9 MBIST User Manual

Functional Description
2-4 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
Restricted Access
2.1.2 MBISTINDATA and MBISTOUTDATA mapping
This section describes how the different RAM arrays are mapped on MBISTINDATA
and MBISTOUTDATA:
• Instruction data and Data data RAMs on page 2-5
• Instruction tag, Data tag and SCU tag RAMs on page 2-6
• Outer RAM on page 2-8
• Branch Target Address Cache RAM on page 2-8
• TLB RAM on page 2-9
• Global History Buffer RAMs on page 2-10.
Instruction data RAM
array 2 (way 1 low)
[5] [31:0] - [31:0] [10:0]
Instruction data RAM
array 1 (way 0 high)
[4] [63:32] - [63:32] [10:0]
Instruction data RAM
array 0 (way 0 low)
[4] [31:0] - [31:0] [10:0]
Instruction tag RAM
array 3
[3] [21:0]] - [53:32] [8:0]
Instruction tag RAM array 2 [3] [21:0] - [21:0] [8:0]
Instruction tag RAM array 1 [2 [21:0] - [53:32] [8:0]
Instruction tag RAM array 0 [2] [21:0] - [21:0] [8:0]
BTAC RAM
target array 1
[1] [63:32] - [63:32] [7:0]
BTAC RAM
control array 1
[1] [27:0] - [27:0] [7:0]
BTAC RAM
target array 0
[0] [63:32] - [63:32] [7:0]
BTAC RAM
control array 0
[0] [27:0] - [27:0] [7:0]
Table 2-2 RAM arrays and MBIST controller interfaces (continued)
RAM Name
MBISTARRAY
bit
MBISTINDATA
bits
MBISTBE
bits
MBISTOUTDATA
bits
Max
address
bits

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST