MBIST Datalog Register
4-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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4.1 About the MBIST Datalog Register
The MBIST Datalog Register records information about failing arrays. The register is
79 bits long for each CPU. Figure 4-1 shows the register format.
Figure 4-1 MBIST Datalog Register format
Field descriptions on page 4-3 describes the register fields in detail.
The datalogs for all CPUs are dumped in parallel through MBISTRESULT[5:2] with:
• MBISTRESULT[5] for CPU3
• MBISTRESULT[4] for CPU2
• MBISTRESULT[3] for CPU1
• MBISTRESULT[2] for CPU0.
Failing address Failing CPU data out
Expected
data seed
78 68 67 4 3 0
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