ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
3-10 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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MaxXAddr
The MaxXAddr field specifies the number of X-address counter bits to use during test.
Table 3-7 shows the MaxXAddr settings.
MaxYAddr
The MaxYAddr field specifies the number of Y-address counter bits to use during test.
Table 3-8 shows the MaxYAddr settings.
Table 3-7 MaxXAddr field encoding
MaxXAddr MBIR[35:32] Number of counter bits
<b0010 Unsupported
b0010 2
b0011 3
b0100 4
b0101 5
b0110 6
b0111 7
b1000 8
b1001 9
b1010 10
>b1010 Reserved
Table 3-8 MaxYAddr field encoding
MaxYAddr MBIR[31:28] Number of counter bits
<b0010 Unsupported
b0010 2
b0011 3
b0100 4
b0101 5

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST