ARM Cortex-A9 MBIST User Manual

Introduction
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 1-7
Restricted Access Non-Confidential
1.3 Product revisions
This section summarizes the differences in functionality between the releases of this
MBIST controller.
r0p0 - r1p0 There are no functionality changes. You must use the correct
corresponding revision of MBIST controller with corresponding
processor revision. For example, use an r1p0 processor with an r1p0
MBIST controller.

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST