ARM Cortex-A9 MBIST User Manual

Introduction
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 1-5
Restricted Access Non-Confidential
Figure 1-4 Cortex-A9 processor MBIST interface
MBISTARRAY
MBISTINDATA
MBISTBE
MBISTADDR
MBISTENABLE
RAM
MBISTENABLE
data1
datan
Other
CPUs
Other
SCU
MBISTDOUT
CE
Din
BWE
ADDR
Qout
Functional path
Pipeline stages
12 3 4 56
denotes a D-type flip flop unless otherwise indicated
datan
data1
data1
datan
CK
___
Active-high D-Type
transparent latch
data1
datan
MBISTWRITEEN
data1
datan
WE

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST