ARM Cortex-A9 MBIST User Manual

Introduction
1-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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1.1 About the MBIST controller
MBIST is the industry-standard method of testing embedded memories. MBIST works
by performing sequences of reads and writes to the memory according to a test
algorithm. Many industry-standard test algorithms exist.
An MBIST controller generates the correct sequence of reads and writes to all locations
of the RAM to ensure that the cells are operating correctly. In doing this, some
additional test coverage is achieved in the address and data paths that the MBIST uses.
You must only use the MBIST controller with the Cortex-A9 processor to perform
memory testing of the Cortex-A9 RAMs.
MBIST mode takes priority over all other modes, for example SCAN, in that the
Cortex-A9 RAMs are only accessible to the MBIST controller when MBIST mode is
activated with the MBISTENABLE pin. You must keep the MBISTENABLE signal
LOW during functional mode, and the AXI interfaces LOW during MBIST mode.
The MBIST controller controls the MBIST testing of the Cortex-A9 RAMs through the
MBIST port of the Cortex-A9 processor. Figure 1-1 shows the Cortex-A9 processor
MBIST configuration.
Figure 1-1 Cortex-A9 MBIST configuration
Cortex-A9 /
A9MP NORAM
MBIST block
Dispatch
unit
MBIST
controller
CPU0 RAMs
CPU1 RAMs
(for MP version)
CPU2 RAMs
(for MP version)
CPU3 RAMs
(for MP version)
SCU RAMs
(for MP version)

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST