ARM Cortex-A9 MBIST User Manual

Signal Descriptions
A-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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A.1 MBIST controller interface signals
Table A-1 shows the MBIST controller interface signals.
Table A-1 MBIST controller interface signals
Signal Type Description
MBISTOUTDATA[255:0] Input MBIST data out, from Cortex-A9 processor
MBISTADDR[10:0] Output MBIST address
MBISTARRAY[19:0] Output MBIST RAM one-hot chip enables, see Table A-2.
MBISTINDATA[63:0] Output MBIST data in, to Cortex-A9 processor
MBISTBE[25:0] Output MBIST write enable
MBISTWRITEEN Output Global write enable
Table A-2 MBISTARRAY one-hot chip enables
MBISTARRAY bit RAM name
0 BTAC RAM control array 0 and target array 0
1 BTAC RAM control array 1 and target array 1
2 Instruction tag RAM arrays 0 and 1
3 Instruction tag RAM arrays 2 and 3
4 Instruction data RAM way 0 (blocks 0 and 1)
5 Instruction data RAM way 1 (blocks 2 and 3)
6 Instruction data RAM way 2 (blocks 4 and 5)
7 Instruction data RAM way 3 (blocks 6 and 7)
8 Global History Buffer
9 TLB RAM array 0
10 TLB RAM array 1
11 Data tag RAM arrays 0 and 1
12 Data tag RAM arrays 2 and 3

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST