ARM Cortex-A9 MBIST User Manual

Signal Descriptions
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. A-3
Restricted Access Non-Confidential
13 Data data RAM way 0 (blocks 0 and 4)
14 Data data RAM way 1 (blocks 1 and 5)
15 Data data RAM way 2 (blocks 2 and 6)
16 Data data RAM way 3 (blocks 3 and 7)
17 Douter RAM
18 SCU tag RAM arrays 0 and 1
19 SCU tag RAM arrays 2 and 3
Table A-2 MBISTARRAY one-hot chip enables (continued)
MBISTARRAY bit RAM name

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST