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General| Brand | ARM |
|---|---|
| Model | CoreLink GIC-600AE |
| Category | Controller |
| Language | English |
Details the revision identification scheme (rxpy) for the GIC-600AE product.
Identifies the target audience for this technical reference manual.
Explains the formatting conventions used in Arm documents for clarity.
Lists supplementary Arm documentation and resources for further information.
Describes the key architectural blocks that form the GIC-600AE implementation.
Details the Arm specifications and protocols the GIC-600AE adheres to.
Summarizes the core services, registers, security, and error correction features.
Describes the Design for Test (DFT) signals available for test modes.
Lists the documentation suite provided with the GIC-600AE product.
Details functional differences and changes across GIC-600AE product revisions.
Explains the Distributor's role as the main communication hub and its interfaces.
Describes the Redistributor's responsibility for PPIs and SGIs for core clusters.
Details the ITS functionality for translating message-based interrupts to LPIs.
Explains the MSI-64 Encapsulator's role in combining DeviceID for GITS_TRANSLATER writes.
Describes the SPI Collator's function in converting SPI wires to messages for the Distributor.
Details the Wake Request block's function in converting AXI4-Stream requests to wake signals.
Explains how the GIC-600AE uses AXI4-Stream interfaces for inter-block communication.
Describes the three structure options (wrap, domain, full) for GIC component hierarchy.
Covers the types of interrupts managed: SGIs, PPIs, SPIs, and LPIs.
Explains interrupt grouping and security status determination for routing.
Details the PPIs and SPIs physical interrupt signals.
Describes the hierarchical scheme for routing interrupts to specific cores using MPIDR.
Covers powering down the GIC-600AE and its cores, using GICR_WAKER and GICR_PWRR.
Details the ITS support for mapping message-based interrupts to LPIs.
Explains memory table locations and access attributes for LPI and ITS translations.
Describes the RAMs used and their protection via SECDED ECC.
Details the PMU for counting GIC events and its counter configuration.
Covers GIC-600AE RAS features including error reporting and handling.
Explains how to configure and manage GIC-600AE in multichip systems.
Details the GIC-600AE address map and register page organization.
Provides a summary of Distributor registers including offsets and descriptions.
Summarizes GICM registers for controlling message-based SPIs.
Lists GICR registers for controlling physical LPIs and Redistributor functions.
Details GICR registers controlling SGIs and PPIs within Redistributors.
Lists GITS registers for controlling the Interrupt Translation Service.
Summarizes GICT registers for trace and debug functions.
Lists GICP registers for the Performance Monitoring Unit (PMU).
Details the FMU registers for managing faults and safety mechanisms.
Introduces FuSa detection features and their integration into GIC-600AE.
Describes the FMU's role in processing faults and managing safety mechanisms.
Explains the GIC-600AE's clocking structure and reset mechanisms for FuSa.
Details the lock-step mechanism used to protect GIC-600AE logic via duplication.
Covers SECDED ECC, address protection, and RAM scrubbing for data integrity.
Describes protection for external interfaces like ACE-Lite, AXI4-Stream, and APB.
Explains protection mechanisms for the internal AXI4-Stream interconnect.
Details protection mechanisms for P-Channel and Q-Channel interfaces.
Describes protection for PPI and SPI interrupt interfaces using parity.
Covers protection for MBIST, ATPG/Scan, and LBIST logic.
Explains how to connect and flag external faults using generic fault inputs.
Summarizes GIC-600AE specific configurations and parameters.
Describes general control signals like clocks and resets for the GIC-600AE.
Details the signals used for power management and control within the GIC-600AE.
Describes the PPI and SPI interrupt input and output signals.
Details the GIC Stream interface signals between CPU clusters and Redistributors.
Provides descriptions for all ACE-Lite subordinate and manager interface signals.
Lists miscellaneous signals including chip ID and PPI ID.
Describes AXI4-Stream interface signals used for communication between GIC components.
Details AXI4-Stream interface signals for communication between chips.
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