ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.9.12 GICP_CFGR, Configuration Information Register
This register returns information about the PMU implementation.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-57: GICP_CFGR bit assignments
31 23 22 21 14 13 8 7 6 5
0
NCTRSIZEReservedReserved
ReservedCAPTURE
Table 5-70: GICP_CFGR bit descriptions
Bits Name Description
[31:23] - Reserved, RAZ
[22] CAPTURE Returns 1, to indicate that the GIC supports capture
[21:14] - Reserved, RAZ
[13:8] SIZE Returns 31, to indicate that the GIC supports 32-bit counters
[7:6] - Reserved, RAZ
[5:0] NCTR Returns 4, to indicate that the GIC provides five counters
5.9.13 GICP_CR, Control Register
This register controls whether all counters are enabled or disabled.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
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