Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
This guarantees a reset flush through the non-resettable flops.
3. Release the resets.
When either:
•
The reset_n or reset_n_fdc signal deasserts, the reset_n_sync signal deasserts
synchronously, followed by the reset_n_fdc_sync signal two clk cycles later.
•
The dbg_reset_n or dbg_reset_n_fdc signal deasserts, the dbg_reset_n_sync signal deasserts
synchronously, followed by the dbg_reset_n_fdc_sync signal two clk cycles later.
6.5.2.3 Warm reset sequence
Follow these steps to initiate a Warm reset of the GIC.
About this task
A Warm reset is a reset that occurs after the component has already been operating for some time.
The reset preserves the state of the PMU and the error records, in both the functional and FuSa
GIC address maps. This state preservation is accomplished by not toggling the dbg_reset_n signals.
Procedure
1. Assert the reset_n_sync and reset_n_fdc_sync signals simultaneously.
reset_n_sync and reset_n_fdc_sync signals assert asynchronously at the same time. To assert
the reset_n_sync and reset_n_fdc_sync signals, both external ports must be asserted.
2. Keep the resets asserted for 16 clk cycles.
This duration guarantees a reset flush through the non-resettable flops.
3. Release the resets.
When either the reset_n or reset_n_fdc signal deasserts, the reset_n_sync signal deasserts
synchronously, followed by the reset_n_fdc_sync signal two clk cycles later.
6.6 Lock-step protection
The GIC-600AE logic is protected by redundant lock-step checking.
The exceptions to this are:
•
The RAMs, which are shared
•
The internal AXI4-Stream interconnect, which uses full duplication
The following figure shows the lock-step for the PPI (Redistributor).
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