Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
Appendix A Signal descriptions
This appendix describes the input and output signals.
A.1 Common control signals
The following table shows the GIC-600AE common control signal set.
Signal definitions
Table A-1: Common control signals
Signal Direction Description
[<domain>]clk Input Clock input
[<domain>]reset_n Input Active-LOW reset
dbg_[<domain>]reset_n Input Active-LOW reset for the PMU and error records.
This signal is only present for the domain that contains the Distributor.
Test signals
Signal Direction Description
dftrstdisable Input Reset disable. Disables the external reset input for test mode. When this signal is HIGH, it forces the internal
active-LOW reset HIGH, bypassing the reset synchronizer.
dftse Input Scan enable. Disables clock gates for test mode.
dftcgen Input Clock gate enable. When this signal is HIGH, it forces all the clock gates on so that all internal clocks always run.
dftramhold Input RAM hold. When this signal is HIGH, it forces all the RAM chip selects LOW, preventing accesses to the RAMs.
MBIST controller signals
Signal Direction Description
[<domain>_]mbistack Output MBIST mode ready.
GIC-600AE acknowledges that it is ready for MBIST testing.
[<domain>_]mbistreq Input MBIST mode request.
Request to GIC-600AE to enable MBIST testing. This signal must be tied LOW during
functional operation.
[<domain>_]nmbistreset Input Resets MBIST logic.
Resets functional logic to enable MBIST operation by an active-LOW signal. This signal
must be tied HIGH during functional operation.
[<domain>_]mbistaddr[variable:0]
13
Input Logical address.
The width is based on the RAM with the largest number of words. You must drive the
most significant bits to zero when accessing RAMs with fewer address bits.
[<domain>_]mbistindata[variable:0]
13
Input Data in.
Write data. Width that is based on the RAM with the largest number of data bits.
[<domain>_]mbistoutdata[variable:0]
13
Output Data out.
Read data. Width that is based on the RAM with the largest number of data bits.
[<domain>_]mbistwriteen Input
[<domain>_]mbistreaden Input
Write control (mbistwriteen) and read control (mbistreaden). No access occurs if both
enables are LOW. It is illegal to activate both enables simultaneously.
13
The variable is configuration-dependent.
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