ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[29] SR Indicates whether the GICM_CLRSPI_SR and GICM_SETSPI_SR registers are present:
0 GICM_CLRSPI_SR and GICM_SETSPI_SR registers are not present
1 GICM_CLRSPI_SR and GICM_SETSPI_SR registers are present (only permitted value when Valid==1)
[28:16] INTID The INTID of the lowest or first SPI that is assigned to the frame
[15:11] - Reserved, RES0
[10:0] NumSPIS Returns the number of SPIs that are assigned to the frame.
5.3.2 GICM_IIDR, Message-based Distributor Implementer Identification
Register
This register provides information about the implementer and revision of the message-based
Distributor page.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.3 Distributor registers (GICM) for message-based SPIs summary on
page 117 for the address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-18: GICM_IIDR bit assignments
Reserved RevisionVariant ImplementerProductID
31 024 1123 1220 19 16 15
Table 5-21: GICM_IIDR bit descriptions
Bits Name Function
[31:24] ProductID Indicates the product ID:
0x03 GIC-600AE
[23:20] - Reserved, RAZ
[19:16] Variant Indicates the major revision, or variant, of the product rmpn identifier:
0x0 r0
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