Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
The P-Channel and Q-Channel are protected with redundant chk signal bits with reverse polarity.
Due to the 4-phase asynchronous nature of the P-Channel and Q-Channel, all signals are checked
individually, except for the pstate signal. With 4-phase handshaking, all assertions must be held
until handshaking feedback is received. Therefore, transient assertions are treated as faults, which
are filtered by the protection logic for reliability. The protection logic prevents these faults from
reaching mission mode logic and causing errors. Permanent faults, or Stuck-At Faults (SAFs), are
detected and flagged.
The following figure shows a high-level Q-Channel example that the GIC blocks employ.
Figure 6-14: Q-Channel protection example
Asynchronous
Q-Channel
controller
qacceptn_chk
qdeny_chk
qactive_chk
The qreqn and qreqn_chk signals are synchronized separately. These signals then pass through
redundant sig_prot blocks, which contain the transient filtering logic and stuck-at checker
counters.
The Q-Channel outputs are passed to the external power controller, or internal GIC LPD, with
a temporal delay no greater than two cycles. The temporal delay can vary from 0-2 cycles, due
to corner cases regarding clock alignment in the ADB. The P-Channel and Q-Channel AMBA
®
extensions allow this variation.
6.10.1 CHK bit timing
There is a hard timing requirement that the Stuck-At Fault (SAF) detection logic imposes.
The skew of the preqn, preqn_chk, qreqn, and qreqn_chk signals must be less than the maximum
skew that the SAF detection logic allows.
Clock Ratio (CR)
Equal to (GIC clock frequency) / (channel controller clock frequency).
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 235 of 268
To Next Page
Loading...