Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.2.7 GICD_DCHIPR, Default Chip Register
This register allows Secure software to access the status of a chip in a multichip system. A single
copy of this register exists on each chip in a multichip configuration.
Configurations
This register is available in all multichip configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
Only accessible by Secure accesses.
Bit descriptions
Figure 5-7: GICD_DCHIPR bit assignments
31 3 1 0
Reserved
4
rt_owner
8 7
PUP
Reserved
Table 5-9: GICD_DCHIPR bit assignments
Bits Name Description Type
[31:8] - Reserved -
[7:4] rt_owner Routing table owner:
Value = 0-maximum chip, in the configuration
RW
[3:1] - Reserved -
[0] PUP Power update in progress:
0 PUP not in progress
1 PUP in progress
RO
5.2.8 GICD_CHIPR<n>, Chip Registers
Each register controls the configuration of the chip in a multichip system. This register exists on
each chip in a multichip configuration and is identified by the chip number.
Configurations
This register is available in all multichip configurations.
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