ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description Type
[0] SIP Scrub in progress.
When read:
0 No scrub in progress
1 Scrub in progress
When written:
0 Abort the scrub
1 Start a scrub
When a scrub is complete, the GIC clears the bit to 0.
RW
5.6.4 GITS_OPR, Operations Register
This register controls cache lock.
Configurations
This register is available in all configurations that have one or more ITS blocks.
Attributes
Width 64-bit
Functional group See 5.6 ITS control register summary on page 136 for the address offset,
type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-32: GITS_OPR bit assignments
EVENT_ID
31 16 15
0
Reserved
DEVICE_ID
63 60 59 52 51
32
Reserved
LOCK_
TYPE
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