Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
collated efficiently. However, the reduced use of the Pending table, results in better latency bounds
under load.
This method of caching means that priorities are associated with an incoming LPI and remain with it
until it is serviced. The GIC does not accept changes in the LPI Property table, until the relevant INV
and SYNC commands are executed through an ITS, GICR_INVLPIR, or GICR_INVALLR.
The GIC-600AE considers priority and enable when choosing data to retain in the cache. However,
pending interrupts always take priority over interrupts that are not pending, so there is no
guarantee that the highest priority interrupt data always remains stored in the cache.
Related information
Distributor configuration on page 30
4.11 Memory access and attributes
The LPI and ITS translations and properties are located in memory tables whose locations are
defined in registers that specify their base address, size, and access attributes.
We recommend that all tables are placed in Normal memory. All ITS tables are private, and after
allocation, only the GIC accesses them. However, the LPI Property table and ITS Command queue
are written to by cores, and read by the GIC.
The following table shows the a<x>cache and a<x>domain signal mappings for the memory
transactions that the GIC generates.
Table 4-4: Memory access registers
Access type Register
Mapping control bit
1
LPI Property table GICR_PROPBASER
LPI Pending table GICR_PENDBASER
GICD_FCTLR.DCC
ITS Device table GITS_BASER0
ITS translation table GITS_BASER0
ITS Collection table GITS_BASER1
ITS Command queue GITS_CBASER
GITS_FCTLR.DCC
The main Cacheability value is derived from the *BASER*.OuterCache field, unless it is zero, in
which case the Cacheability value is a value that the following table shows.
Table 4-5: Cacheability values
Main Cacheability value
(*BASER*.OuterCache)
Other Cacheability
value
(*BASER*.InnerCache)
arcache
signal
awcache
signal
arcache
signal
(DCC = 1)
awcache
signal
(DCC = 1)
0b000, Device-nGnRnE - 0b0010 0b0010 0b0010 0b0010
1
The mappings are designed for the Armv8 and Armv8.2 generation of cores. However, setting this bit converts the
GIC-600AE to full featured mapping.
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